| Message ID | 20200610052416.116684-1-ley.foon.tan@intel.com |
|---|---|
| State | Accepted |
| Commit | a0bda1dd8382be57389833024ba40518ec098ac3 |
| Headers | show |
| Series | [v2] arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns | expand |
On 6/10/20 7:24 AM, Ley Foon Tan wrote: > Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing calculation") > change the hcnt and lcnt timing calculation. New timing calculation is > based on calculation from Designware i2c databook. > > After this new timing calculation, hcnt will have negative value > with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts. > > This patch overwrite i2c-scl-falling-time-ns to 300ns (default SCL fall > time used in Designware i2c driver) for Uboot. Applied, thanks.
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi index 7d9874cafa0b..d24f621cd669 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi @@ -68,3 +68,7 @@ &portc { bank-name = "portc"; }; + +&i2c0 { + i2c-scl-falling-time-ns = <300>; +};
Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing calculation") change the hcnt and lcnt timing calculation. New timing calculation is based on calculation from Designware i2c databook. After this new timing calculation, hcnt will have negative value with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts. This patch overwrite i2c-scl-falling-time-ns to 300ns (default SCL fall time used in Designware i2c driver) for Uboot. Before the fix: => i2c dev 0 Setting bus to 0 Failure changing bus number (-22) After the fix: => i2c dev 0 Setting bus to 0 => i2c probe Valid chip addresses: 17 51 55 5B 5C 5E 66 68 70 Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com> --- v2: - Mentioned new timing calculation is from databook in commit message. --- arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)