| Message ID | 1391607050-540-4-git-send-email-marc.zyngier@arm.com |
|---|---|
| State | New |
| Headers | show |
On Wed, Feb 05, 2014 at 01:30:35PM +0000, Marc Zyngier wrote: > Linux has some requirements that must be satisfied in order to boot > on a system built with a GICv3. > > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> There are some patches I haven't acked in this series, so here it goes: Acked-by: Catalin Marinas <catalin.marinas@arm.com>
On 25/02/14 18:06, Will Deacon wrote: > On Wed, Feb 05, 2014 at 01:30:35PM +0000, Marc Zyngier wrote: >> Linux has some requirements that must be satisfied in order to boot >> on a system built with a GICv3. >> >> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> >> --- >> Documentation/arm64/booting.txt | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt >> index a9691cc..4a02ebd 100644 >> --- a/Documentation/arm64/booting.txt >> +++ b/Documentation/arm64/booting.txt >> @@ -131,6 +131,13 @@ Before jumping into the kernel, the following conditions must be met: >> the kernel image will be entered must be initialised by software at a >> higher exception level to prevent execution in an UNKNOWN state. >> >> + For systems with a GICv3 interrupt controller, it is expected that: >> + - ID_AA64PFR0_EL1.GIC (bits [27:24]) must have the value 0b0001 > > Since ID_AA64PFR0_EL1 is read-only at all exception levels, I don't see the > value of this statement. Think virtualization. A hypervisor can control reads of ID_AA64PFR0_EL1 by setting HCR_EL2.TID3, and report whatever it wants. >> + - If EL3 is present, it must program ICC_SRE_EL3.Enable (bit 3) to >> + 0b1 and ICC_SRE_EL3.SRE (bit 0) to 0b1. >> + - If the kernel is entered at EL1, EL2 must set ICC_SRE_EL2.Enable >> + (bit 3) to 0b1 and ICC_SRE_EL2.SRE (bit 0) to 0b1. > > Does this force the kernel to use SRE? No. The kernel still have to explicitly set ICC_SRE_EL1.SRE to 1. Cheers, M.
On 26/02/14 15:31, Will Deacon wrote: > On Wed, Feb 26, 2014 at 02:37:00PM +0000, Marc Zyngier wrote: >> On 25/02/14 18:06, Will Deacon wrote: >>> On Wed, Feb 05, 2014 at 01:30:35PM +0000, Marc Zyngier wrote: >>>> Linux has some requirements that must be satisfied in order to boot >>>> on a system built with a GICv3. >>>> >>>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> >>>> --- >>>> Documentation/arm64/booting.txt | 7 +++++++ >>>> 1 file changed, 7 insertions(+) >>>> >>>> diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt >>>> index a9691cc..4a02ebd 100644 >>>> --- a/Documentation/arm64/booting.txt >>>> +++ b/Documentation/arm64/booting.txt >>>> @@ -131,6 +131,13 @@ Before jumping into the kernel, the following conditions must be met: >>>> the kernel image will be entered must be initialised by software at a >>>> higher exception level to prevent execution in an UNKNOWN state. >>>> >>>> + For systems with a GICv3 interrupt controller, it is expected that: >>>> + - ID_AA64PFR0_EL1.GIC (bits [27:24]) must have the value 0b0001 >>> >>> Since ID_AA64PFR0_EL1 is read-only at all exception levels, I don't see the >>> value of this statement. >> >> Think virtualization. A hypervisor can control reads of ID_AA64PFR0_EL1 >> by setting HCR_EL2.TID3, and report whatever it wants. > > Sure, but it seems unreasonable to me that we require a hypervisor to tell a > guest about GICv3 if the system happens to have one. What if it wants to > emulate a GICv2? In other words, requiring this in booting.txt seems > superflous. The hypervisor can perfectly mask out the GICv3 feature if it wants to. The point I'm trying to make here is that if a guest is expected to be able to use the GICv3 system registers, then ID_AA64PFR0_EL1 should report so. M.
diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index a9691cc..4a02ebd 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -131,6 +131,13 @@ Before jumping into the kernel, the following conditions must be met: the kernel image will be entered must be initialised by software at a higher exception level to prevent execution in an UNKNOWN state. + For systems with a GICv3 interrupt controller, it is expected that: + - ID_AA64PFR0_EL1.GIC (bits [27:24]) must have the value 0b0001 + - If EL3 is present, it must program ICC_SRE_EL3.Enable (bit 3) to + 0b1 and ICC_SRE_EL3.SRE (bit 0) to 0b1. + - If the kernel is entered at EL1, EL2 must set ICC_SRE_EL2.Enable + (bit 3) to 0b1 and ICC_SRE_EL2.SRE (bit 0) to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level.
Linux has some requirements that must be satisfied in order to boot on a system built with a GICv3. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- Documentation/arm64/booting.txt | 7 +++++++ 1 file changed, 7 insertions(+)