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[v3,2/4] riscv: dts: hifive-unleashed-a00: add cpu aliases

Message ID 1591267479-8900-3-git-send-email-sagar.kadam@sifive.com
State Superseded
Headers show
Series update clock handler and proper cpu features | expand

Commit Message

Sagar Shrikant Kadam June 4, 2020, 10:44 a.m. UTC 
Add cpu aliases to U-Boot specific dtsi for hifive-unleashed.
Without aliases we see that the CPU device sequence numbers are set
randomly and the cpu list/detail command will show it as follows:
=> cpu list
  1: cpu at 0      rv64imac
  0: cpu at 1      rv64imafdc
  2: cpu at 2      rv64imafdc
  3: cpu at 3      rv64imafdc
  4: cpu at 4      rv64imafdc

Seems like CPU probing with dm-model also relies on aliases as observed
in case spi. The fu540-c000-u-boot.dtsi has cpu0/1/2/3/4 nodes and so
adding corresponding aliases we can ensure that cpu devices are assigned
proper sequence as follows:

=> cpu list
  0: cpu at 0      rv64imac
  1: cpu at 1      rv64imafdc
  2: cpu at 2      rv64imafdc
  3: cpu at 3      rv64imafdc
  4: cpu at 4      rv64imafdc

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel at sifive.com>
---
 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +++++
 1 file changed, 5 insertions(+)
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Patch

diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 9787332..9894260 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -7,6 +7,11 @@ 
 
 / {
 	aliases {
+		cpu0 = &cpu0;
+		cpu1 = &cpu1;
+		cpu2 = &cpu2;
+		cpu3 = &cpu3;
+		cpu4 = &cpu4;
 		spi0 = &qspi0;
 		spi2 = &qspi2;
 	};