diff mbox series

[v2,3/3] clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()

Message ID 20200117120642.97362-4-giulio.benetti@benettiengineering.com
State Accepted
Commit 041b06a7c32f596f00dd495444a1b02568a9d492
Headers show
Series fix pllv3 defects reported by Coverity | expand

Commit Message

Giulio Benetti Jan. 17, 2020, 12:06 p.m. UTC 
Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL.

Signed-off-by: Giulio Benetti <giulio.benetti at benettiengineering.com>
---
V1->V2
* check only if parent_rate==0, as signalled by Adam
---
 drivers/clk/imx/clk-pllv3.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 72e6750615..0cdb9df45d 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -176,13 +176,19 @@  static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
 {
 	struct clk_pllv3 *pll = to_clk_pllv3(clk);
 	unsigned long parent_rate = clk_get_parent_rate(clk);
-	unsigned long min_rate = parent_rate * 27;
-	unsigned long max_rate = parent_rate * 54;
+	unsigned long min_rate;
+	unsigned long max_rate;
 	u32 val, div;
 	u32 mfn, mfd = 1000000;
 	u32 max_mfd = 0x3FFFFFFF;
 	u64 temp64;
 
+	if (parent_rate == 0)
+		return -EINVAL;
+
+	min_rate = parent_rate * 27;
+	max_rate = parent_rate * 54;
+
 	if (rate < min_rate || rate > max_rate)
 		return -EINVAL;