diff mbox series

net: zynq_gem: Use ulong instead of u32 data type

Message ID 302a03b42a9bc997db7c4e473bac404fa79fd8dc.1579161277.git.michal.simek@xilinx.com
State Accepted
Commit b6779274f2bdbcde2c7fa3a2f90d1db55c02951f
Headers show
Series net: zynq_gem: Use ulong instead of u32 data type | expand

Commit Message

Michal Simek Jan. 16, 2020, 7:54 a.m. UTC 
From: T Karthik Reddy <t.karthik.reddy at xilinx.com>

flush_dcache_range() expects unsigned long in the arguments. Here u32
variable is unable to hold the higher address value when ddr mapped
to higher addresses & flushing lower address dchache range instead
which is unmapped causing to crash.

Signed-off-by: T Karthik Reddy <t.karthik.reddy at xilinx.com>
Signed-off-by: Michal Simek <michal.simek at xilinx.com>
---

 drivers/net/zynq_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index c3fe8e3c563f..879129653df3 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -653,7 +653,7 @@  static int zynq_gem_probe(struct udevice *dev)
 		return -ENOMEM;
 
 	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
-	u32 addr = (ulong)priv->rxbuffers;
+	ulong addr = (ulong)priv->rxbuffers;
 	flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
 	barrier();