[v3] reset: socfpga: Poll for reset status after deassert reset

In Cyclone 5 SoC platform, the first USB probing is failed but second
probing is success. DWC2 USB driver read gsnpsid register right after
de-assert reset, but controller is not ready yet and it returns gsnpsid 0.
Polling reset status after de-assert reset to solve the issue.

Retry with this fix more than 10 times without issue.

Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>

---
v3:
- Remove _status callback and poll reset status after deassert reset

v2:
- https://patchwork.ozlabs.org/cover/1215174/

v1:
- https://patchwork.ozlabs.org/patch/1214841/
---
 drivers/reset/reset-socfpga.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

Hi Ley,

On Mon, 6 Jan 2020 at 01:09, Ley Foon Tan <ley.foon.tan at intel.com> wrote:
>
> In Cyclone 5 SoC platform, the first USB probing is failed but second
> probing is success. DWC2 USB driver read gsnpsid register right after
> de-assert reset, but controller is not ready yet and it returns gsnpsid 0.
> Polling reset status after de-assert reset to solve the issue.
>
> Retry with this fix more than 10 times without issue.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
>
> ---
> v3:
> - Remove _status callback and poll reset status after deassert reset
>
> v2:
> - https://patchwork.ozlabs.org/cover/1215174/
>
> v1:
> - https://patchwork.ozlabs.org/patch/1214841/
> ---
>  drivers/reset/reset-socfpga.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
> index 93ec9cfdb6..172028dcf6 100644
> --- a/drivers/reset/reset-socfpga.c
> +++ b/drivers/reset/reset-socfpga.c
> @@ -78,9 +78,20 @@ static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
>         int reg_width = sizeof(u32);
>         int bank = id / (reg_width * BITS_PER_BYTE);
>         int offset = id % (reg_width * BITS_PER_BYTE);
> +       int i = 1000;
> +       u32 status;
>
>         clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
> -       return 0;
> +
> +       /* Poll until reset is completed. */
> +       do {
> +               status = readl(data->modrst_base + (bank * BANK_INCREMENT)) &
> +                              BIT(offset);
> +               if (!status)
> +                       return 0;
> +       } while (i--);

This should be something like:

start = get_timer(0);
while (1) {
    existing code
    if (get_timer(start) > TIMEOUT_MS)
        return -ETIMEOUT;
    };

so that you actually have a timeout. At present the timeout is indeterminate.

> +
> +       return -ETIMEDOUT;
>  }
>
>  static int socfpga_reset_request(struct reset_ctl *reset_ctl)
> --
> 2.19.0
>

Regards,
Simon

> -----Original Message-----
> From: Simon Glass <sjg at chromium.org>
> Sent: Wednesday, January 8, 2020 12:50 AM
> To: Tan, Ley Foon <ley.foon.tan at intel.com>
> Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Marek Vasut
> <marex at denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt at gmail.com>; Joe Hershberger
> <joe.hershberger at ni.com>; Ley Foon Tan <lftan.linux at gmail.com>; See,
> Chin Liang <chin.liang.see at intel.com>; Chee, Tien Fong
> <tien.fong.chee at intel.com>
> Subject: Re: [PATCH v3] reset: socfpga: Poll for reset status after deassert
> reset
> 
> Hi Ley,
> 
> On Mon, 6 Jan 2020 at 01:09, Ley Foon Tan <ley.foon.tan at intel.com> wrote:
> >
> > In Cyclone 5 SoC platform, the first USB probing is failed but second
> > probing is success. DWC2 USB driver read gsnpsid register right after
> > de-assert reset, but controller is not ready yet and it returns gsnpsid 0.
> > Polling reset status after de-assert reset to solve the issue.
> >
> > Retry with this fix more than 10 times without issue.
> >
> > Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
> >
> > ---
> > v3:
> > - Remove _status callback and poll reset status after deassert reset
> >
> > v2:
> > - https://patchwork.ozlabs.org/cover/1215174/
> >
> > v1:
> > - https://patchwork.ozlabs.org/patch/1214841/
> > ---
> >  drivers/reset/reset-socfpga.c | 13 ++++++++++++-
> >  1 file changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/reset/reset-socfpga.c
> > b/drivers/reset/reset-socfpga.c index 93ec9cfdb6..172028dcf6 100644
> > --- a/drivers/reset/reset-socfpga.c
> > +++ b/drivers/reset/reset-socfpga.c
> > @@ -78,9 +78,20 @@ static int socfpga_reset_deassert(struct reset_ctl
> *reset_ctl)
> >         int reg_width = sizeof(u32);
> >         int bank = id / (reg_width * BITS_PER_BYTE);
> >         int offset = id % (reg_width * BITS_PER_BYTE);
> > +       int i = 1000;
> > +       u32 status;
> >
> >         clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT),
> BIT(offset));
> > -       return 0;
> > +
> > +       /* Poll until reset is completed. */
> > +       do {
> > +               status = readl(data->modrst_base + (bank * BANK_INCREMENT))
> &
> > +                              BIT(offset);
> > +               if (!status)
> > +                       return 0;
> > +       } while (i--);
> 
> This should be something like:
> 
> start = get_timer(0);
> while (1) {
>     existing code
>     if (get_timer(start) > TIMEOUT_MS)
>         return -ETIMEOUT;
>     };
> 
> so that you actually have a timeout. At present the timeout is indeterminate.

Okay, will change it.

Thanks.

Regards
Ley Foon