| Message ID | 20200430100619.28557-2-patrice.chotard@st.com |
|---|---|
| State | Accepted |
| Commit | 84f8e36f03fafa7e2e2ff822db90fefa6bd5f350 |
| Headers | show |
| Series | cmd: bind allow to bind driver with driver_data | expand |
On Thu, Apr 30, 2020 at 12:06:15PM +0200, Patrice Chotard wrote: > Initial implementation invokes device_bind_with_driver_data() > with driver_data parameter equal to 0. > For driver with driver data, the bind command can't bind > correctly this driver or even worse causes data abort as shown below: > > As example, for debug purpose on STM32MP1 platform, ethernet (dwc_eth_qos.c) > driver needed to be unbinded/binded. This driver is using driver data: > > static const struct udevice_id eqos_ids[] = { > { > .compatible = "nvidia,tegra186-eqos", > .data = (ulong)&eqos_tegra186_config > }, > { > .compatible = "snps,dwmac-4.20a", > .data = (ulong)&eqos_stm32_config > }, > > { } > }; > > After unbinding/binding this driver and probing it (with the dhcp command), > we got a prefetch abort as below: > > STM32MP> unbind eth ethernet at 5800a000 > STM32MP> bind /soc/ethernet at 5800a000 eth_eqos > STM32MP> dhcp > prefetch abort > pc : [<4310801c>] lr : [<ffc8f4ad>] > reloc pc : [<035ba01c>] lr : [<c01414ad>] > sp : fdaf19b0 ip : ffcea83c fp : 00000001 > r10: ffcfd4a0 r9 : fdaffed0 r8 : 00000000 > r7 : ffcff304 r6 : fdc63220 r5 : 00000000 r4 : fdc5b108 > r3 : 43108020 r2 : 00003d39 r1 : ffcea544 r0 : fdc63220 > Flags: nZCv IRQs off FIQs off Mode SVC_32 > Code: data abort > pc : [<ffc4f9c0>] lr : [<ffc4f9ad>] > reloc pc : [<c01019c0>] lr : [<c01019ad>] > sp : fdaf18b8 ip : 00000000 fp : 00000001 > r10: ffcd69b2 r9 : fdaffed0 r8 : ffcd69aa > r7 : 00000000 r6 : 00000008 r5 : 4310801c r4 : fffffffc > r3 : 00000001 r2 : 00000028 r1 : 00000000 r0 : 00000006 > Flags: NzCv IRQs on FIQs on Mode SVC_32 (T) > Code: 2f00 d1e9 2c00 dce9 (f855) 2024 > Resetting CPU ... > > Signed-off-by: Patrice Chotard <patrice.chotard at st.com> > Cc: Jean-Jacques Hiblot <jjhiblot at ti.com> > Reviewed-by: Simon Glass <sjg at chromium.org> Sorry for the delay in getting to this. Currently, this breaks the dm unit tests on sandbox, can you please investigate? Thanks!
Hi Tom Sorry for the delay, i was on vacation. I launched dm unit tests on current master (ada61f1ee2a4eaa1b29d699b5ba940483171df8a) and everything seems ok, perhaps i don't execute them correctly, see my log below : ./test/py/test.py --bd sandbox --build -k ut_dm -v +make O=/local/home/nxp11987/projects/community/u-boot.denx/build-sandbox -s sandbox_defconfig +make O=/local/home/nxp11987/projects/community/u-boot.denx/build-sandbox -s -j8 ======================================================================================= test session starts ======================================================================================= platform linux -- Python 3.6.9, pytest-5.2.1, py-1.8.0, pluggy-0.13.0 -- /usr/bin/python3 cachedir: .pytest_cache rootdir: /local/home/nxp11987/projects/community/u-boot.denx/test/py, inifile: pytest.ini collected 672 items / 370 deselected / 302 selected test/py/tests/test_ut.py::test_ut_dm_init PASSED [ 0%] test/py/tests/test_ut.py::test_ut[ut_dm_acpi_basic] PASSED [ 0%] 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test/py/tests/test_ut.py::test_ut[ut_dm_phy_base] PASSED [ 66%] test/py/tests/test_ut.py::test_ut[ut_dm_phy_bulk] PASSED [ 66%] test/py/tests/test_ut.py::test_ut[ut_dm_phy_ops] PASSED [ 66%] test/py/tests/test_ut.py::test_ut[ut_dm_platdata] PASSED [ 67%] test/py/tests/test_ut.py::test_ut[ut_dm_pmc_base] PASSED [ 67%] test/py/tests/test_ut.py::test_ut[ut_dm_power_domain] PASSED [ 67%] test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_get] PASSED [ 68%] test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_io] PASSED [ 68%] test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_mc34708_get] PASSED [ 68%] test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_mc34708_regs_check] PASSED [ 69%] test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_mc34708_rw_val] PASSED [ 69%] test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_autoset] PASSED [ 69%] test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_autoset_list] PASSED [ 70%] test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_get] PASSED [ 70%] test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_enable_if_allowed] PASSED [ 70%] test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_current] PASSED [ 71%] test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_enable] PASSED [ 71%] test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_mode] PASSED [ 71%] test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_suspend_enable] PASSED [ 72%] test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_suspend_voltage] PASSED [ 72%] test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_voltage] PASSED [ 72%] test/py/tests/test_ut.py::test_ut[ut_dm_pre_reloc] PASSED [ 73%] test/py/tests/test_ut.py::test_ut[ut_dm_pwm_base] PASSED [ 73%] test/py/tests/test_ut.py::test_ut[ut_dm_ram_base] PASSED [ 73%] test/py/tests/test_ut.py::test_ut[ut_dm_read_and_clear] PASSED [ 74%] test/py/tests/test_ut.py::test_ut[ut_dm_read_int] PASSED [ 74%] test/py/tests/test_ut.py::test_ut[ut_dm_read_int_index] PASSED [ 74%] test/py/tests/test_ut.py::test_ut[ut_dm_regmap_base] PASSED [ 75%] test/py/tests/test_ut.py::test_ut[ut_dm_regmap_getset] PASSED [ 75%] test/py/tests/test_ut.py::test_ut[ut_dm_regmap_poll] PASSED [ 75%] test/py/tests/test_ut.py::test_ut[ut_dm_regmap_rw] PASSED [ 76%] test/py/tests/test_ut.py::test_ut[ut_dm_regmap_syscon] PASSED [ 76%] test/py/tests/test_ut.py::test_ut[ut_dm_remoteproc_base] PASSED [ 76%] test/py/tests/test_ut.py::test_ut[ut_dm_remoteproc_elf] PASSED [ 77%] test/py/tests/test_ut.py::test_ut[ut_dm_remove] PASSED [ 77%] test/py/tests/test_ut.py::test_ut[ut_dm_remove_active_dma] PASSED [ 77%] test/py/tests/test_ut.py::test_ut[ut_dm_request] PASSED [ 78%] test/py/tests/test_ut.py::test_ut[ut_dm_reset] PASSED [ 78%] test/py/tests/test_ut.py::test_ut[ut_dm_reset_base] PASSED [ 78%] test/py/tests/test_ut.py::test_ut[ut_dm_reset_bulk] PASSED [ 79%] test/py/tests/test_ut.py::test_ut[ut_dm_rng_read] PASSED [ 79%] test/py/tests/test_ut.py::test_ut[ut_dm_rtc_base] PASSED [ 79%] test/py/tests/test_ut.py::test_ut[ut_dm_rtc_cmd_list] PASSED [ 80%] test/py/tests/test_ut.py::test_ut[ut_dm_rtc_cmd_rw] PASSED [ 80%] test/py/tests/test_ut.py::test_ut[ut_dm_rtc_dual] PASSED [ 80%] test/py/tests/test_ut.py::test_ut[ut_dm_rtc_read_write] PASSED [ 81%] test/py/tests/test_ut.py::test_ut[ut_dm_rtc_reset] PASSED [ 81%] test/py/tests/test_ut.py::test_ut[ut_dm_rtc_set_get] PASSED [ 81%] test/py/tests/test_ut.py::test_ut[ut_dm_serial] PASSED [ 82%] test/py/tests/test_ut.py::test_ut[ut_dm_simple_pm_bus] PASSED [ 82%] test/py/tests/test_ut.py::test_ut[ut_dm_smem_base] PASSED [ 82%] test/py/tests/test_ut.py::test_ut[ut_dm_sound] PASSED [ 83%] test/py/tests/test_ut.py::test_ut[ut_dm_sound_beep] PASSED [ 83%] test/py/tests/test_ut.py::test_ut[ut_dm_spi_find] PASSED [ 83%] test/py/tests/test_ut.py::test_ut[ut_dm_spi_flash] PASSED [ 84%] test/py/tests/test_ut.py::test_ut[ut_dm_spi_flash_func] PASSED [ 84%] test/py/tests/test_ut.py::test_ut[ut_dm_spi_xfer] PASSED [ 84%] test/py/tests/test_ut.py::test_ut[ut_dm_spmi_access] PASSED [ 85%] test/py/tests/test_ut.py::test_ut[ut_dm_spmi_access_peripheral] PASSED [ 85%] test/py/tests/test_ut.py::test_ut[ut_dm_spmi_probe] PASSED [ 85%] test/py/tests/test_ut.py::test_ut[ut_dm_syscon_base] PASSED [ 86%] test/py/tests/test_ut.py::test_ut[ut_dm_syscon_by_driver_data] PASSED [ 86%] test/py/tests/test_ut.py::test_ut[ut_dm_syscon_by_phandle] PASSED [ 86%] test/py/tests/test_ut.py::test_ut[ut_dm_syscon_reset] PASSED [ 87%] test/py/tests/test_ut.py::test_ut[ut_dm_sysreset_base] PASSED [ 87%] test/py/tests/test_ut.py::test_ut[ut_dm_sysreset_get_last] PASSED [ 87%] test/py/tests/test_ut.py::test_ut[ut_dm_sysreset_get_status] PASSED [ 88%] test/py/tests/test_ut.py::test_ut[ut_dm_sysreset_walk] PASSED [ 88%] test/py/tests/test_ut.py::test_ut[ut_dm_tee] PASSED [ 88%] test/py/tests/test_ut.py::test_ut[ut_dm_timer_base] PASSED [ 89%] test/py/tests/test_ut.py::test_ut[ut_dm_uclass] PASSED [ 89%] test/py/tests/test_ut.py::test_ut[ut_dm_uclass_before_ready] PASSED [ 89%] test/py/tests/test_ut.py::test_ut[ut_dm_uclass_devices_find] PASSED [ 90%] test/py/tests/test_ut.py::test_ut[ut_dm_uclass_devices_find_by_name] PASSED [ 90%] test/py/tests/test_ut.py::test_ut[ut_dm_uclass_devices_get] PASSED [ 90%] test/py/tests/test_ut.py::test_ut[ut_dm_uclass_devices_get_by_name] PASSED [ 91%] test/py/tests/test_ut.py::test_ut[ut_dm_uclass_drvdata] PASSED [ 91%] test/py/tests/test_ut.py::test_ut[ut_dm_uclass_foreach] PASSED [ 91%] test/py/tests/test_ut.py::test_ut[ut_dm_uclass_names] PASSED [ 92%] test/py/tests/test_ut.py::test_ut[ut_dm_usb_base] PASSED [ 92%] test/py/tests/test_ut.py::test_ut[ut_dm_usb_fdt_node] PASSED [ 92%] test/py/tests/test_ut.py::test_ut[ut_dm_usb_flash] PASSED [ 93%] test/py/tests/test_ut.py::test_ut[ut_dm_usb_keyb] PASSED [ 93%] test/py/tests/test_ut.py::test_ut[ut_dm_usb_multi] PASSED [ 93%] test/py/tests/test_ut.py::test_ut[ut_dm_usb_stop] PASSED [ 94%] test/py/tests/test_ut.py::test_ut[ut_dm_video_ansi] PASSED [ 94%] test/py/tests/test_ut.py::test_ut[ut_dm_video_base] PASSED [ 94%] test/py/tests/test_ut.py::test_ut[ut_dm_video_bmp] PASSED [ 95%] test/py/tests/test_ut.py::test_ut[ut_dm_video_bmp_comp] PASSED [ 95%] test/py/tests/test_ut.py::test_ut[ut_dm_video_chars] PASSED [ 95%] test/py/tests/test_ut.py::test_ut[ut_dm_video_context] PASSED [ 96%] test/py/tests/test_ut.py::test_ut[ut_dm_video_rotation1] PASSED [ 96%] test/py/tests/test_ut.py::test_ut[ut_dm_video_rotation2] PASSED [ 96%] test/py/tests/test_ut.py::test_ut[ut_dm_video_rotation3] PASSED [ 97%] test/py/tests/test_ut.py::test_ut[ut_dm_video_text] PASSED [ 97%] test/py/tests/test_ut.py::test_ut[ut_dm_video_truetype] PASSED [ 97%] test/py/tests/test_ut.py::test_ut[ut_dm_video_truetype_bs] PASSED [ 98%] test/py/tests/test_ut.py::test_ut[ut_dm_video_truetype_scroll] PASSED [ 98%] test/py/tests/test_ut.py::test_ut[ut_dm_virtio_all_ops] PASSED [ 98%] test/py/tests/test_ut.py::test_ut[ut_dm_virtio_base] PASSED [ 99%] test/py/tests/test_ut.py::test_ut[ut_dm_virtio_missing_ops] PASSED [ 99%] test/py/tests/test_ut.py::test_ut[ut_dm_virtio_remove] PASSED [ 99%] test/py/tests/test_ut.py::test_ut[ut_dm_wdt_base] PASSED [100%] ============================================================================== 302 passed, 370 deselected in 11.06s =============================================================================== Patrice On 7/7/20 10:08 PM, Tom Rini wrote: > On Thu, Apr 30, 2020 at 12:06:15PM +0200, Patrice Chotard wrote: > >> Initial implementation invokes device_bind_with_driver_data() >> with driver_data parameter equal to 0. >> For driver with driver data, the bind command can't bind >> correctly this driver or even worse causes data abort as shown below: >> >> As example, for debug purpose on STM32MP1 platform, ethernet (dwc_eth_qos.c) >> driver needed to be unbinded/binded. This driver is using driver data: >> >> static const struct udevice_id eqos_ids[] = { >> { >> .compatible = "nvidia,tegra186-eqos", >> .data = (ulong)&eqos_tegra186_config >> }, >> { >> .compatible = "snps,dwmac-4.20a", >> .data = (ulong)&eqos_stm32_config >> }, >> >> { } >> }; >> >> After unbinding/binding this driver and probing it (with the dhcp command), >> we got a prefetch abort as below: >> >> STM32MP> unbind eth ethernet@5800a000 >> STM32MP> bind /soc/ethernet@5800a000 eth_eqos >> STM32MP> dhcp >> prefetch abort >> pc : [<4310801c>] lr : [<ffc8f4ad>] >> reloc pc : [<035ba01c>] lr : [<c01414ad>] >> sp : fdaf19b0 ip : ffcea83c fp : 00000001 >> r10: ffcfd4a0 r9 : fdaffed0 r8 : 00000000 >> r7 : ffcff304 r6 : fdc63220 r5 : 00000000 r4 : fdc5b108 >> r3 : 43108020 r2 : 00003d39 r1 : ffcea544 r0 : fdc63220 >> Flags: nZCv IRQs off FIQs off Mode SVC_32 >> Code: data abort >> pc : [<ffc4f9c0>] lr : [<ffc4f9ad>] >> reloc pc : [<c01019c0>] lr : [<c01019ad>] >> sp : fdaf18b8 ip : 00000000 fp : 00000001 >> r10: ffcd69b2 r9 : fdaffed0 r8 : ffcd69aa >> r7 : 00000000 r6 : 00000008 r5 : 4310801c r4 : fffffffc >> r3 : 00000001 r2 : 00000028 r1 : 00000000 r0 : 00000006 >> Flags: NzCv IRQs on FIQs on Mode SVC_32 (T) >> Code: 2f00 d1e9 2c00 dce9 (f855) 2024 >> Resetting CPU ... >> >> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> >> Cc: Jean-Jacques Hiblot <jjhiblot@ti.com> >> Reviewed-by: Simon Glass <sjg@chromium.org> > Sorry for the delay in getting to this. Currently, this breaks the dm > unit tests on sandbox, can you please investigate? Thanks! >
On Mon, Jul 27, 2020 at 02:25:06PM +0000, Patrice CHOTARD wrote: > Hi Tom > > Sorry for the delay, i was on vacation. > > I launched dm unit tests on current master (ada61f1ee2a4eaa1b29d699b5ba940483171df8a) > > and everything seems ok, perhaps i don't execute them correctly, see my log below : > > ./test/py/test.py --bd sandbox --build -k ut_dm -v > Hunh, alright. The series isn't applying cleanly for me either, so can you please rebase and repost? It seems I must have messed something up in the rebase. Thanks! -- Tom
don't take care of my previous email, i did a mistake .... Patrice On 7/27/20 4:25 PM, Patrice CHOTARD wrote: > Hi Tom > > Sorry for the delay, i was on vacation. > > I launched dm unit tests on current master (ada61f1ee2a4eaa1b29d699b5ba940483171df8a) > > and everything seems ok, perhaps i don't execute them correctly, see my log below : > > ./test/py/test.py --bd sandbox --build -k ut_dm -v > > +make O=/local/home/nxp11987/projects/community/u-boot.denx/build-sandbox -s sandbox_defconfig > +make O=/local/home/nxp11987/projects/community/u-boot.denx/build-sandbox -s -j8 > ======================================================================================= test session starts ======================================================================================= > platform linux -- Python 3.6.9, pytest-5.2.1, py-1.8.0, pluggy-0.13.0 -- /usr/bin/python3 > cachedir: .pytest_cache > rootdir: /local/home/nxp11987/projects/community/u-boot.denx/test/py, inifile: pytest.ini > collected 672 items / 370 deselected / 302 selected > > test/py/tests/test_ut.py::test_ut_dm_init PASSED [ 0%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_basic] PASSED [ 0%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_cmd_dump] PASSED [ 0%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_cmd_items] PASSED [ 1%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_cmd_list] PASSED [ 1%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_create_dmar] PASSED [ 1%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_device] PASSED [ 2%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_device_path] PASSED [ 2%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_device_status] PASSED [ 2%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_dp_array] PASSED [ 3%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_dp_child] PASSED [ 3%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_dp_copy] PASSED [ 3%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_dp_gpio] PASSED [ 4%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_dp_int] PASSED [ 4%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_dp_int16] PASSED [ 4%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_dp_int64] PASSED [ 5%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_dp_int8] PASSED [ 5%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_dp_multiple] PASSED [ 5%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_dp_new_table] PASSED [ 6%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_emit_simple] PASSED [ 6%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_emit_stream] PASSED [ 6%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_emit_string] PASSED [ 7%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_fill_header] PASSED [ 7%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_fill_ssdt] PASSED [ 7%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_get_name] PASSED [ 8%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_get_table_revision] PASSED [ 8%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_gpio] PASSED [ 8%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_gpio_irq] PASSED [ 9%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_gpio_toggle] PASSED [ 9%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_i2c] PASSED [ 9%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_inject_dsdt] PASSED [ 10%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_integer] PASSED [ 10%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_interrupt] PASSED [ 10%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_interrupt_or_gpio] PASSED [ 11%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_len] PASSED [ 11%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_misc] PASSED [ 11%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_name] PASSED [ 12%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_package] PASSED [ 12%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_power_res] PASSED [ 12%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_power_seq] PASSED [ 13%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_resource_template] PASSED [ 13%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_scope] PASSED [ 13%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_setup_base_tables] PASSED [ 14%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_spi] PASSED [ 14%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_string] PASSED [ 14%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_uuid] PASSED [ 15%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_write_name] PASSED [ 15%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_write_tables] PASSED [ 15%] > test/py/tests/test_ut.py::test_ut[ut_dm_acpi_write_values] PASSED [ 16%] > test/py/tests/test_ut.py::test_ut[ut_dm_adc_bind] PASSED [ 16%] > test/py/tests/test_ut.py::test_ut[ut_dm_adc_multi_channel_conversion] PASSED [ 16%] > test/py/tests/test_ut.py::test_ut[ut_dm_adc_multi_channel_shot] PASSED [ 17%] > test/py/tests/test_ut.py::test_ut[ut_dm_adc_raw_to_uV] PASSED [ 17%] > test/py/tests/test_ut.py::test_ut[ut_dm_adc_single_channel_conversion] PASSED [ 17%] > test/py/tests/test_ut.py::test_ut[ut_dm_adc_single_channel_shot] PASSED [ 18%] > test/py/tests/test_ut.py::test_ut[ut_dm_adc_supply] PASSED [ 18%] > test/py/tests/test_ut.py::test_ut[ut_dm_adc_wrong_channel_selection] PASSED [ 18%] > test/py/tests/test_ut.py::test_ut[ut_dm_alias_highest_id] PASSED [ 19%] > test/py/tests/test_ut.py::test_ut[ut_dm_audio] PASSED [ 19%] > test/py/tests/test_ut.py::test_ut[ut_dm_autobind] PASSED [ 19%] > test/py/tests/test_ut.py::test_ut[ut_dm_autobind_uclass_pdata_alloc] PASSED [ 20%] > test/py/tests/test_ut.py::test_ut[ut_dm_autobind_uclass_pdata_valid] PASSED [ 20%] > test/py/tests/test_ut.py::test_ut[ut_dm_autoprobe] PASSED [ 20%] > test/py/tests/test_ut.py::test_ut[ut_dm_axi_base] PASSED [ 21%] > test/py/tests/test_ut.py::test_ut[ut_dm_axi_busnum] PASSED [ 21%] > test/py/tests/test_ut.py::test_ut[ut_dm_axi_store] PASSED [ 21%] > test/py/tests/test_ut.py::test_ut[ut_dm_blk_base] PASSED [ 22%] > test/py/tests/test_ut.py::test_ut[ut_dm_blk_devnum] PASSED [ 22%] > test/py/tests/test_ut.py::test_ut[ut_dm_blk_find] PASSED [ 22%] > test/py/tests/test_ut.py::test_ut[ut_dm_blk_get_from_parent] PASSED [ 23%] > test/py/tests/test_ut.py::test_ut[ut_dm_blk_usb] PASSED [ 23%] > test/py/tests/test_ut.py::test_ut[ut_dm_board] PASSED [ 23%] > test/py/tests/test_ut.py::test_ut[ut_dm_bootcount] PASSED [ 24%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_child_post_bind] PASSED [ 24%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_child_post_bind_uclass] PASSED [ 24%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_child_post_probe_uclass] PASSED [ 25%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_child_pre_probe_uclass] PASSED [ 25%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_children] PASSED [ 25%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_children_funcs] PASSED [ 26%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_children_iterators] PASSED [ 26%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_children_of_offset] PASSED [ 26%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_data] PASSED [ 27%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_data_uclass] PASSED [ 27%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_ops] PASSED [ 27%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_platdata] PASSED [ 28%] > test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_platdata_uclass] PASSED [ 28%] > test/py/tests/test_ut.py::test_ut[ut_dm_child_ofdata] PASSED [ 28%] > test/py/tests/test_ut.py::test_ut[ut_dm_children] PASSED [ 29%] > test/py/tests/test_ut.py::test_ut[ut_dm_clk] PASSED [ 29%] > test/py/tests/test_ut.py::test_ut[ut_dm_clk_base] PASSED [ 29%] > test/py/tests/test_ut.py::test_ut[ut_dm_clk_bulk] PASSED [ 30%] > test/py/tests/test_ut.py::test_ut[ut_dm_clk_ccf] PASSED [ 30%] > test/py/tests/test_ut.py::test_ut[ut_dm_cpu] PASSED [ 30%] > test/py/tests/test_ut.py::test_ut[ut_dm_device_get_uclass_id] PASSED [ 31%] > test/py/tests/test_ut.py::test_ut[ut_dm_devres_alloc] PASSED [ 31%] > test/py/tests/test_ut.py::test_ut[ut_dm_devres_free] PASSED [ 31%] > test/py/tests/test_ut.py::test_ut[ut_dm_devres_kcalloc] PASSED [ 32%] > test/py/tests/test_ut.py::test_ut[ut_dm_devres_kmalloc_array] PASSED [ 32%] > test/py/tests/test_ut.py::test_ut[ut_dm_devres_kzalloc] PASSED [ 32%] > test/py/tests/test_ut.py::test_ut[ut_dm_devres_phase] PASSED [ 33%] > test/py/tests/test_ut.py::test_ut[ut_dm_dma] PASSED [ 33%] > test/py/tests/test_ut.py::test_ut[ut_dm_dma_m2m] PASSED [ 33%] > test/py/tests/test_ut.py::test_ut[ut_dm_dma_rx] PASSED [ 34%] > test/py/tests/test_ut.py::test_ut[ut_dm_dsi_host] PASSED [ 34%] > test/py/tests/test_ut.py::test_ut[ut_dm_eth] PASSED [ 34%] > test/py/tests/test_ut.py::test_ut[ut_dm_eth_act] PASSED [ 35%] > test/py/tests/test_ut.py::test_ut[ut_dm_eth_alias] PASSED [ 35%] > test/py/tests/test_ut.py::test_ut[ut_dm_eth_async_arp_reply] PASSED [ 35%] > test/py/tests/test_ut.py::test_ut[ut_dm_eth_async_ping_reply] PASSED [ 36%] > test/py/tests/test_ut.py::test_ut[ut_dm_eth_prime] PASSED [ 36%] > test/py/tests/test_ut.py::test_ut[ut_dm_eth_rotate] PASSED [ 36%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt] PASSED [ 37%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_disable_enable_by_path] PASSED [ 37%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_livetree_writing] PASSED [ 37%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_offset] PASSED [ 38%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_phandle] PASSED [ 38%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_pre_reloc] PASSED [ 38%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_remap_addr_flat] PASSED [ 39%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_remap_addr_index_flat] PASSED [ 39%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_remap_addr_index_live] PASSED [ 39%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_remap_addr_live] PASSED [ 40%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_remap_addr_name_flat] PASSED [ 40%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_remap_addr_name_live] PASSED [ 40%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_translation] PASSED [ 41%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdt_uclass_seq] PASSED [ 41%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdtdec_add_reserved_memory] PASSED [ 41%] > test/py/tests/test_ut.py::test_ut[ut_dm_fdtdec_set_carveout] PASSED [ 42%] > test/py/tests/test_ut.py::test_ut[ut_dm_firmware_probe] PASSED [ 42%] > test/py/tests/test_ut.py::test_ut[ut_dm_first_child] PASSED [ 42%] > test/py/tests/test_ut.py::test_ut[ut_dm_first_child_probe] PASSED [ 43%] > test/py/tests/test_ut.py::test_ut[ut_dm_first_next_device] PASSED [ 43%] > test/py/tests/test_ut.py::test_ut[ut_dm_first_next_ok_device] PASSED [ 43%] > test/py/tests/test_ut.py::test_ut[ut_dm_gpio] PASSED [ 44%] > test/py/tests/test_ut.py::test_ut[ut_dm_gpio_anon] PASSED [ 44%] > test/py/tests/test_ut.py::test_ut[ut_dm_gpio_copy] PASSED [ 44%] > test/py/tests/test_ut.py::test_ut[ut_dm_gpio_get_acpi] PASSED [ 45%] > test/py/tests/test_ut.py::test_ut[ut_dm_gpio_get_acpi_irq] PASSED [ 45%] > test/py/tests/test_ut.py::test_ut[ut_dm_gpio_get_dir_flags] PASSED [ 45%] > test/py/tests/test_ut.py::test_ut[ut_dm_gpio_leak] PASSED [ 46%] > test/py/tests/test_ut.py::test_ut[ut_dm_gpio_opendrain_opensource] PASSED [ 46%] > test/py/tests/test_ut.py::test_ut[ut_dm_gpio_phandles] PASSED [ 46%] > test/py/tests/test_ut.py::test_ut[ut_dm_gpio_requestf] PASSED [ 47%] > test/py/tests/test_ut.py::test_ut[ut_dm_hwspinlock_base] PASSED [ 47%] > test/py/tests/test_ut.py::test_ut[ut_dm_i2c_addr_offset] PASSED [ 47%] > test/py/tests/test_ut.py::test_ut[ut_dm_i2c_bytewise] PASSED [ 48%] > test/py/tests/test_ut.py::test_ut[ut_dm_i2c_find] PASSED [ 48%] > test/py/tests/test_ut.py::test_ut[ut_dm_i2c_offset] PASSED [ 48%] > test/py/tests/test_ut.py::test_ut[ut_dm_i2c_offset_len] PASSED [ 49%] > test/py/tests/test_ut.py::test_ut[ut_dm_i2c_probe_empty] PASSED [ 49%] > test/py/tests/test_ut.py::test_ut[ut_dm_i2c_read_write] PASSED [ 49%] > test/py/tests/test_ut.py::test_ut[ut_dm_i2c_speed] PASSED [ 50%] > test/py/tests/test_ut.py::test_ut[ut_dm_i2s] PASSED [ 50%] > test/py/tests/test_ut.py::test_ut[ut_dm_inactive_child] PASSED [ 50%] > test/py/tests/test_ut.py::test_ut[ut_dm_irq_base] PASSED [ 50%] > test/py/tests/test_ut.py::test_ut[ut_dm_irq_get_acpi] PASSED [ 51%] > test/py/tests/test_ut.py::test_ut[ut_dm_irq_type] PASSED [ 51%] > test/py/tests/test_ut.py::test_ut[ut_dm_leak] PASSED [ 51%] > test/py/tests/test_ut.py::test_ut[ut_dm_led_base] PASSED [ 52%] > test/py/tests/test_ut.py::test_ut[ut_dm_led_blink] PASSED [ 52%] > test/py/tests/test_ut.py::test_ut[ut_dm_led_default_state] PASSED [ 52%] > test/py/tests/test_ut.py::test_ut[ut_dm_led_gpio] PASSED [ 53%] > test/py/tests/test_ut.py::test_ut[ut_dm_led_label] PASSED [ 53%] > test/py/tests/test_ut.py::test_ut[ut_dm_led_toggle] PASSED [ 53%] > test/py/tests/test_ut.py::test_ut[ut_dm_lifecycle] PASSED [ 54%] > test/py/tests/test_ut.py::test_ut[ut_dm_mailbox] PASSED [ 54%] > test/py/tests/test_ut.py::test_ut[ut_dm_mdio] PASSED [ 54%] > test/py/tests/test_ut.py::test_ut[ut_dm_mdio_mux] PASSED [ 55%] > test/py/tests/test_ut.py::test_ut[ut_dm_misc] PASSED [ 55%] > test/py/tests/test_ut.py::test_ut[ut_dm_mmc_base] PASSED [ 55%] > test/py/tests/test_ut.py::test_ut[ut_dm_mmc_blk] PASSED [ 56%] > test/py/tests/test_ut.py::test_ut[ut_dm_net_retry] PASSED [ 56%] > test/py/tests/test_ut.py::test_ut[ut_dm_nop] PASSED [ 56%] > test/py/tests/test_ut.py::test_ut[ut_dm_ofdata_order] PASSED [ 57%] > test/py/tests/test_ut.py::test_ut[ut_dm_ofnode_by_prop_value] PASSED [ 57%] > test/py/tests/test_ut.py::test_ut[ut_dm_ofnode_compatible] PASSED [ 57%] > test/py/tests/test_ut.py::test_ut[ut_dm_ofnode_fmap] PASSED [ 58%] > test/py/tests/test_ut.py::test_ut[ut_dm_ofnode_get_child_count] PASSED [ 58%] > test/py/tests/test_ut.py::test_ut[ut_dm_ofnode_get_property_by_prop] PASSED [ 58%] > test/py/tests/test_ut.py::test_ut[ut_dm_ofnode_read] PASSED [ 59%] > test/py/tests/test_ut.py::test_ut[ut_dm_ofnode_read_chosen] PASSED [ 59%] > test/py/tests/test_ut.py::test_ut[ut_dm_operations] PASSED [ 59%] > test/py/tests/test_ut.py::test_ut[ut_dm_ordering] PASSED [ 60%] > test/py/tests/test_ut.py::test_ut[ut_dm_osd_basics] PASSED [ 60%] > test/py/tests/test_ut.py::test_ut[ut_dm_osd_extended] PASSED [ 60%] > test/py/tests/test_ut.py::test_ut[ut_dm_p2sb_base] PASSED [ 61%] > test/py/tests/test_ut.py::test_ut[ut_dm_panel] PASSED [ 61%] > test/py/tests/test_ut.py::test_ut[ut_dm_pch_base] PASSED [ 61%] > test/py/tests/test_ut.py::test_ut[ut_dm_pch_ioctl] PASSED [ 62%] > test/py/tests/test_ut.py::test_ut[ut_dm_pci_addr_flat] PASSED [ 62%] > test/py/tests/test_ut.py::test_ut[ut_dm_pci_addr_live] PASSED [ 62%] > test/py/tests/test_ut.py::test_ut[ut_dm_pci_base] PASSED [ 63%] > test/py/tests/test_ut.py::test_ut[ut_dm_pci_busdev] PASSED [ 63%] > test/py/tests/test_ut.py::test_ut[ut_dm_pci_cap] PASSED [ 63%] > test/py/tests/test_ut.py::test_ut[ut_dm_pci_drvdata] PASSED [ 64%] > test/py/tests/test_ut.py::test_ut[ut_dm_pci_ea] PASSED [ 64%] > test/py/tests/test_ut.py::test_ut[ut_dm_pci_ep_base] PASSED [ 64%] > test/py/tests/test_ut.py::test_ut[ut_dm_pci_mixed] PASSED [ 65%] > test/py/tests/test_ut.py::test_ut[ut_dm_pci_on_bus] PASSED [ 65%] > test/py/tests/test_ut.py::test_ut[ut_dm_pci_swapcase] PASSED [ 65%] > test/py/tests/test_ut.py::test_ut[ut_dm_phy_base] PASSED [ 66%] > test/py/tests/test_ut.py::test_ut[ut_dm_phy_bulk] PASSED �� [ 66%] > test/py/tests/test_ut.py::test_ut[ut_dm_phy_ops] PASSED [ 66%] > test/py/tests/test_ut.py::test_ut[ut_dm_platdata] PASSED [ 67%] > test/py/tests/test_ut.py::test_ut[ut_dm_pmc_base] PASSED [ 67%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_domain] PASSED [ 67%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_get] PASSED [ 68%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_io] PASSED [ 68%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_mc34708_get] PASSED [ 68%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_mc34708_regs_check] PASSED [ 69%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_mc34708_rw_val] PASSED [ 69%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_autoset] PASSED [ 69%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_autoset_list] PASSED [ 70%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_get] PASSED [ 70%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_enable_if_allowed] PASSED [ 70%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_current] PASSED [ 71%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_enable] PASSED [ 71%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_mode] PASSED [ 71%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_suspend_enable] PASSED [ 72%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_suspend_voltage] PASSED [ 72%] > test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_voltage] PASSED [ 72%] > test/py/tests/test_ut.py::test_ut[ut_dm_pre_reloc] PASSED [ 73%] > test/py/tests/test_ut.py::test_ut[ut_dm_pwm_base] PASSED [ 73%] > test/py/tests/test_ut.py::test_ut[ut_dm_ram_base] PASSED [ 73%] > test/py/tests/test_ut.py::test_ut[ut_dm_read_and_clear] PASSED [ 74%] > test/py/tests/test_ut.py::test_ut[ut_dm_read_int] PASSED [ 74%] > test/py/tests/test_ut.py::test_ut[ut_dm_read_int_index] PASSED [ 74%] > test/py/tests/test_ut.py::test_ut[ut_dm_regmap_base] PASSED [ 75%] > test/py/tests/test_ut.py::test_ut[ut_dm_regmap_getset] PASSED [ 75%] > test/py/tests/test_ut.py::test_ut[ut_dm_regmap_poll] PASSED [ 75%] > test/py/tests/test_ut.py::test_ut[ut_dm_regmap_rw] PASSED [ 76%] > test/py/tests/test_ut.py::test_ut[ut_dm_regmap_syscon] PASSED [ 76%] > test/py/tests/test_ut.py::test_ut[ut_dm_remoteproc_base] PASSED [ 76%] > test/py/tests/test_ut.py::test_ut[ut_dm_remoteproc_elf] PASSED [ 77%] > test/py/tests/test_ut.py::test_ut[ut_dm_remove] PASSED [ 77%] > test/py/tests/test_ut.py::test_ut[ut_dm_remove_active_dma] PASSED [ 77%] > test/py/tests/test_ut.py::test_ut[ut_dm_request] PASSED [ 78%] > test/py/tests/test_ut.py::test_ut[ut_dm_reset] PASSED [ 78%] > test/py/tests/test_ut.py::test_ut[ut_dm_reset_base] PASSED [ 78%] > test/py/tests/test_ut.py::test_ut[ut_dm_reset_bulk] PASSED [ 79%] > test/py/tests/test_ut.py::test_ut[ut_dm_rng_read] PASSED [ 79%] > test/py/tests/test_ut.py::test_ut[ut_dm_rtc_base] PASSED [ 79%] > test/py/tests/test_ut.py::test_ut[ut_dm_rtc_cmd_list] PASSED [ 80%] > test/py/tests/test_ut.py::test_ut[ut_dm_rtc_cmd_rw] PASSED [ 80%] > test/py/tests/test_ut.py::test_ut[ut_dm_rtc_dual] PASSED [ 80%] > test/py/tests/test_ut.py::test_ut[ut_dm_rtc_read_write] PASSED [ 81%] > test/py/tests/test_ut.py::test_ut[ut_dm_rtc_reset] PASSED [ 81%] > test/py/tests/test_ut.py::test_ut[ut_dm_rtc_set_get] PASSED [ 81%] > test/py/tests/test_ut.py::test_ut[ut_dm_serial] PASSED [ 82%] > test/py/tests/test_ut.py::test_ut[ut_dm_simple_pm_bus] PASSED [ 82%] > test/py/tests/test_ut.py::test_ut[ut_dm_smem_base] PASSED [ 82%] > test/py/tests/test_ut.py::test_ut[ut_dm_sound] PASSED [ 83%] > test/py/tests/test_ut.py::test_ut[ut_dm_sound_beep] PASSED [ 83%] > test/py/tests/test_ut.py::test_ut[ut_dm_spi_find] PASSED [ 83%] > test/py/tests/test_ut.py::test_ut[ut_dm_spi_flash] PASSED [ 84%] > test/py/tests/test_ut.py::test_ut[ut_dm_spi_flash_func] PASSED [ 84%] > test/py/tests/test_ut.py::test_ut[ut_dm_spi_xfer] PASSED [ 84%] > test/py/tests/test_ut.py::test_ut[ut_dm_spmi_access] PASSED [ 85%] > test/py/tests/test_ut.py::test_ut[ut_dm_spmi_access_peripheral] PASSED [ 85%] > test/py/tests/test_ut.py::test_ut[ut_dm_spmi_probe] PASSED [ 85%] > test/py/tests/test_ut.py::test_ut[ut_dm_syscon_base] PASSED [ 86%] > test/py/tests/test_ut.py::test_ut[ut_dm_syscon_by_driver_data] PASSED [ 86%] > test/py/tests/test_ut.py::test_ut[ut_dm_syscon_by_phandle] PASSED [ 86%] > test/py/tests/test_ut.py::test_ut[ut_dm_syscon_reset] PASSED [ 87%] > test/py/tests/test_ut.py::test_ut[ut_dm_sysreset_base] PASSED [ 87%] > test/py/tests/test_ut.py::test_ut[ut_dm_sysreset_get_last] PASSED [ 87%] > test/py/tests/test_ut.py::test_ut[ut_dm_sysreset_get_status] PASSED [ 88%] > test/py/tests/test_ut.py::test_ut[ut_dm_sysreset_walk] PASSED [ 88%] > test/py/tests/test_ut.py::test_ut[ut_dm_tee] PASSED [ 88%] > test/py/tests/test_ut.py::test_ut[ut_dm_timer_base] PASSED [ 89%] > test/py/tests/test_ut.py::test_ut[ut_dm_uclass] PASSED [ 89%] > test/py/tests/test_ut.py::test_ut[ut_dm_uclass_before_ready] PASSED [ 89%] > test/py/tests/test_ut.py::test_ut[ut_dm_uclass_devices_find] PASSED [ 90%] > test/py/tests/test_ut.py::test_ut[ut_dm_uclass_devices_find_by_name] PASSED [ 90%] > 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PASSED [ 99%] > test/py/tests/test_ut.py::test_ut[ut_dm_wdt_base] PASSED [100%] > > ============================================================================== 302 passed, 370 deselected in 11.06s =============================================================================== > > > Patrice > > On 7/7/20 10:08 PM, Tom Rini wrote: >> On Thu, Apr 30, 2020 at 12:06:15PM +0200, Patrice Chotard wrote: >> >>> Initial implementation invokes device_bind_with_driver_data() >>> with driver_data parameter equal to 0. >>> For driver with driver data, the bind command can't bind >>> correctly this driver or even worse causes data abort as shown below: >>> >>> As example, for debug purpose on STM32MP1 platform, ethernet (dwc_eth_qos.c) >>> driver needed to be unbinded/binded. This driver is using driver data: >>> >>> static const struct udevice_id eqos_ids[] = { >>> { >>> .compatible = "nvidia,tegra186-eqos", >>> .data = (ulong)&eqos_tegra186_config >>> }, >>> { >>> .compatible = "snps,dwmac-4.20a", >>> .data = (ulong)&eqos_stm32_config >>> }, >>> >>> { } >>> }; >>> >>> After unbinding/binding this driver and probing it (with the dhcp command), >>> we got a prefetch abort as below: >>> >>> STM32MP> unbind eth ethernet@5800a000 >>> STM32MP> bind /soc/ethernet@5800a000 eth_eqos >>> STM32MP> dhcp >>> prefetch abort >>> pc : [<4310801c>] lr : [<ffc8f4ad>] >>> reloc pc : [<035ba01c>] lr : [<c01414ad>] >>> sp : fdaf19b0 ip : ffcea83c fp : 00000001 >>> r10: ffcfd4a0 r9 : fdaffed0 r8 : 00000000 >>> r7 : ffcff304 r6 : fdc63220 r5 : 00000000 r4 : fdc5b108 >>> r3 : 43108020 r2 : 00003d39 r1 : ffcea544 r0 : fdc63220 >>> Flags: nZCv IRQs off FIQs off Mode SVC_32 >>> Code: data abort >>> pc : [<ffc4f9c0>] lr : [<ffc4f9ad>] >>> reloc pc : [<c01019c0>] lr : [<c01019ad>] >>> sp : fdaf18b8 ip : 00000000 fp : 00000001 >>> r10: ffcd69b2 r9 : fdaffed0 r8 : ffcd69aa >>> r7 : 00000000 r6 : 00000008 r5 : 4310801c r4 : fffffffc >>> r3 : 00000001 r2 : 00000028 r1 : 00000000 r0 : 00000006 >>> Flags: NzCv IRQs on FIQs on Mode SVC_32 (T) >>> Code: 2f00 d1e9 2c00 dce9 (f855) 2024 >>> Resetting CPU ... >>> >>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> >>> Cc: Jean-Jacques Hiblot <jjhiblot@ti.com> >>> Reviewed-by: Simon Glass <sjg@chromium.org> >> Sorry for the delay in getting to this. Currently, this breaks the dm >> unit tests on sandbox, can you please investigate? Thanks! > >
Hi Tom On 7/7/20 10:08 PM, Tom Rini wrote: > On Thu, Apr 30, 2020 at 12:06:15PM +0200, Patrice Chotard wrote: > >> Initial implementation invokes device_bind_with_driver_data() >> with driver_data parameter equal to 0. >> For driver with driver data, the bind command can't bind >> correctly this driver or even worse causes data abort as shown below: >> >> As example, for debug purpose on STM32MP1 platform, ethernet (dwc_eth_qos.c) >> driver needed to be unbinded/binded. This driver is using driver data: >> >> static const struct udevice_id eqos_ids[] = { >> { >> .compatible = "nvidia,tegra186-eqos", >> .data = (ulong)&eqos_tegra186_config >> }, >> { >> .compatible = "snps,dwmac-4.20a", >> .data = (ulong)&eqos_stm32_config >> }, >> >> { } >> }; >> >> After unbinding/binding this driver and probing it (with the dhcp command), >> we got a prefetch abort as below: >> >> STM32MP> unbind eth ethernet@5800a000 >> STM32MP> bind /soc/ethernet@5800a000 eth_eqos >> STM32MP> dhcp >> prefetch abort >> pc : [<4310801c>] lr : [<ffc8f4ad>] >> reloc pc : [<035ba01c>] lr : [<c01414ad>] >> sp : fdaf19b0 ip : ffcea83c fp : 00000001 >> r10: ffcfd4a0 r9 : fdaffed0 r8 : 00000000 >> r7 : ffcff304 r6 : fdc63220 r5 : 00000000 r4 : fdc5b108 >> r3 : 43108020 r2 : 00003d39 r1 : ffcea544 r0 : fdc63220 >> Flags: nZCv IRQs off FIQs off Mode SVC_32 >> Code: data abort >> pc : [<ffc4f9c0>] lr : [<ffc4f9ad>] >> reloc pc : [<c01019c0>] lr : [<c01019ad>] >> sp : fdaf18b8 ip : 00000000 fp : 00000001 >> r10: ffcd69b2 r9 : fdaffed0 r8 : ffcd69aa >> r7 : 00000000 r6 : 00000008 r5 : 4310801c r4 : fffffffc >> r3 : 00000001 r2 : 00000028 r1 : 00000000 r0 : 00000006 >> Flags: NzCv IRQs on FIQs on Mode SVC_32 (T) >> Code: 2f00 d1e9 2c00 dce9 (f855) 2024 >> Resetting CPU ... >> >> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> >> Cc: Jean-Jacques Hiblot <jjhiblot@ti.com> >> Reviewed-by: Simon Glass <sjg@chromium.org> > Sorry for the delay in getting to this. Currently, this breaks the dm > unit tests on sandbox, can you please investigate? Thanks! > A v5 has been submitted fixing the dm unit test regression Thanks Patrice
diff --git a/cmd/bind.c b/cmd/bind.c index 44a5f17f0d..0aefc531d8 100644 --- a/cmd/bind.c +++ b/cmd/bind.c @@ -7,6 +7,7 @@ #include <dm.h> #include <dm/device-internal.h> #include <dm/lists.h> +#include <dm/root.h> #include <dm/uclass-internal.h> static int bind_by_class_index(const char *uclass, int index, @@ -150,8 +151,8 @@ static int bind_by_node_path(const char *path, const char *drv_name) } ofnode = ofnode_path(path); - ret = device_bind_with_driver_data(parent, drv, ofnode_get_name(ofnode), - 0, ofnode, &dev); + ret = lists_bind_fdt(parent, ofnode, &dev, false); + if (!dev || ret) { printf("Unable to bind. err:%d\n", ret); return ret;
Initial implementation invokes device_bind_with_driver_data() with driver_data parameter equal to 0. For driver with driver data, the bind command can't bind correctly this driver or even worse causes data abort as shown below: As example, for debug purpose on STM32MP1 platform, ethernet (dwc_eth_qos.c) driver needed to be unbinded/binded. This driver is using driver data: static const struct udevice_id eqos_ids[] = { { .compatible = "nvidia,tegra186-eqos", .data = (ulong)&eqos_tegra186_config }, { .compatible = "snps,dwmac-4.20a", .data = (ulong)&eqos_stm32_config }, { } }; After unbinding/binding this driver and probing it (with the dhcp command), we got a prefetch abort as below: STM32MP> unbind eth ethernet at 5800a000 STM32MP> bind /soc/ethernet at 5800a000 eth_eqos STM32MP> dhcp prefetch abort pc : [<4310801c>] lr : [<ffc8f4ad>] reloc pc : [<035ba01c>] lr : [<c01414ad>] sp : fdaf19b0 ip : ffcea83c fp : 00000001 r10: ffcfd4a0 r9 : fdaffed0 r8 : 00000000 r7 : ffcff304 r6 : fdc63220 r5 : 00000000 r4 : fdc5b108 r3 : 43108020 r2 : 00003d39 r1 : ffcea544 r0 : fdc63220 Flags: nZCv IRQs off FIQs off Mode SVC_32 Code: data abort pc : [<ffc4f9c0>] lr : [<ffc4f9ad>] reloc pc : [<c01019c0>] lr : [<c01019ad>] sp : fdaf18b8 ip : 00000000 fp : 00000001 r10: ffcd69b2 r9 : fdaffed0 r8 : ffcd69aa r7 : 00000000 r6 : 00000008 r5 : 4310801c r4 : fffffffc r3 : 00000001 r2 : 00000028 r1 : 00000000 r0 : 00000006 Flags: NzCv IRQs on FIQs on Mode SVC_32 (T) Code: 2f00 d1e9 2c00 dce9 (f855) 2024 Resetting CPU ... Signed-off-by: Patrice Chotard <patrice.chotard at st.com> Cc: Jean-Jacques Hiblot <jjhiblot at ti.com> Reviewed-by: Simon Glass <sjg at chromium.org> --- Changes in v4: None Changes in v3: None Changes in v2: - add a bind command test - add bind command documentation in doc/driver/model/bind.rst - simplify patch 1 by using lists_bind_fdt() cmd/bind.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)