[v1,16/49] arm: dts: ns3: add PAXB PCIe host and phy node

Message ID	20200427105207.5659-17-rayagonda.kokatanur@broadcom.com
State	Superseded
Headers	show List-Id: U-Boot discussion <u-boot.lists.denx.de> From: rayagonda.kokatanur at broadcom.com (Rayagonda Kokatanur) Date: Mon, 27 Apr 2020 16:21:34 +0530 Subject: [PATCH v1 16/49] arm: dts: ns3: add PAXB PCIe host and phy node In-Reply-To: <20200427105207.5659-1-rayagonda.kokatanur@broadcom.com> References: <20200427105207.5659-1-rayagonda.kokatanur@broadcom.com> Message-ID: <20200427105207.5659-17-rayagonda.kokatanur@broadcom.com>
Series	add support for broadcom NS3 soc \| expand [v1,00/49] add support for broadcom NS3 soc [v1,01/49] board: ns3: add support for Broadcom Northstar 3 [v1,02/49] arm: cpu: armv8: add L3 memory flush support [v1,03/49] configs: ns3: enable clock subsystem [v1,04/49] arm: dts: ns3: add clock dt node [v1,05/49] configs: ns3: enable pinctrl driver [v1,06/49] dt-bindings: pinctrl: add ns3 pads definition [v1,07/49] arm: dts: ns3: add pinctrl node [v1,08/49] arm: dts: ns3: add gpio node [v1,09/49] gpio: do not include <asm/arch/gpio.h> on TARGET_BCMNS3 [v1,10/49] configs: ns3: enable BCM IPROC mmc driver [v1,11/49] arm: dts: ns3: add emmc node [v1,12/49] configs: ns3: enable mmc commands [v1,13/49] arm: dts: ns3: add qspi node [v1,14/49] dt-bindings: memory: ns3: add memory definitions [v1,15/49] arm: dts: ns3: add i2c node [v1,16/49] arm: dts: ns3: add PAXB PCIe host and phy node [v1,17/49] configs: ns3: enable gpt commands [v1,18/49] configs: ns3: enable EXT4 and FAT fs support [v1,19/49] configs: ns3: enable sp805 watchdog driver [v1,20/49] arm: dts: ns3: add sp805 watchdog node [v1,21/49] board: ns3: start sp805 watchdog service [v1,22/49] board: ns3: add api to save boot parameters passed from BL31 [v1,23/49] board: ns3: default reset type to L3 [v1,24/49] dt-bindings: memory: ns3: update GIC LPI address [v1,25/49] board: ns3: program GIC LPI tables [v1,26/49] configs: ns3: enable GIC ITS LPI table programing [v1,27/49] dt-bindings: memory: ns3: add ddr memory definition [v1,28/49] board: ns3: define ddr memory layout [v1,29/49] board: ns3: limit U-boot relocation within 16MB memory [v1,30/49] configs: ns3: enable FIT config [v1,31/49] board: ns3: add FIT image its file [v1,32/49] board: ns3: add development keys used in FIT [v1,33/49] configs: ns3: enable PXE boot command [v1,34/49] configs: ns3: enable RPMB [v1,35/49] board: ns3: add optee based bnxt fw load driver [v1,36/49] configs: ns3: enable tee and optee driver [v1,37/49] arm: dts: ns3: add optee node [v1,38/49] board: ns3: add generic MCU IPC command send API [v1,39/49] include/configs: ns3: add env variables for Linux boot [v1,40/49] configs: ns3: env in mmc [v1,41/49] include/configs: ns3: add support for flashing images [v1,42/49] common: ns3: add error logging support [v1,43/49] board: ns3: kconfig: extend board kconfig with specific commands [v1,44/49] cmd: bcm: add broadcom error log setup command [v1,45/49] cmd: gpt: add eMMC and GPT support [v1,46/49] cmd: bcm: add nitro boot command [v1,47/49] cmd: bcm: add nitro image load commands [v1,48/49] cmd: bcm: add command for chimp hand shake [v1,49/49] board: ns3: check chimp handshake status

diff --git a/arch/arm/dts/ns3-board.dts b/arch/arm/dts/ns3-board.dts index 1155ff3ef1..ce5012dc52 100644 --- a/arch/arm/dts/ns3-board.dts +++ b/arch/arm/dts/ns3-board.dts @@ -44,3 +44,39 @@ &sdio0 { status = "okay"; }; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&pcie3 { + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie5 { + status = "okay"; +}; + +&pcie6 { + status = "okay"; +}; + +&pcie7 { + status = "okay"; +}; + +&pcie8 { + status = "okay"; +}; diff --git a/arch/arm/dts/ns3.dtsi b/arch/arm/dts/ns3.dtsi index adb1277471..9fd59a855e 100644 --- a/arch/arm/dts/ns3.dtsi +++ b/arch/arm/dts/ns3.dtsi @@ -5,6 +5,11 @@ #include "skeleton64.dtsi" +#define PCIE_DMA_RANGES dma-ranges = < \ + 0x43000000 0x00 0x80000000 0x00 0x80000000 0x00 0x80000000 \ + 0x43000000 0x08 0x00000000 0x08 0x00000000 0x08 0x00000000 \ + 0x43000000 0x80 0x00000000 0x80 0x00000000 0x80 0x00000000> + / { compatible = "brcm,ns3"; #address-cells = <2>; @@ -89,4 +94,157 @@ <&pinmux 145 149 6>; }; }; + + pcie0: pcie at 48000000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x48000000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0x0 0x42000000 0x0 0x42000000 0 0x2000000>, + <0x43000000 0x4 0x00000000 0x4 0x00000000 0 0x80000000>; + brcm,pcie-ob; + PCIE_DMA_RANGES; + phys = <&pcie_phy 0>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie1: pcie at 48004000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x48004000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0x0 0x44000000 0x0 0x44000000 0 0x2000000>, + <0x43000000 0x4 0x80000000 0x4 0x80000000 0 0x80000000>; + brcm,pcie-ob; + PCIE_DMA_RANGES; + phys = <&pcie_phy 1>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie2: pcie at 48008000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x48008000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0x0 0x4a000000 0x0 0x4a000000 0 0x2000000>, + <0x43000000 0x5 0x00000000 0x5 0x00000000 0 0x80000000>; + brcm,pcie-ob; + PCIE_DMA_RANGES; + phys = <&pcie_phy 2>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie3: pcie at 4800c000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x4800c000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + brcm,pcie-ob; + ranges = <0x83000000 0x0 0x4c000000 0x0 0x4c000000 0 0x2000000>, + <0x43000000 0x5 0x80000000 0x5 0x80000000 0 0x80000000>; + PCIE_DMA_RANGES; + phys = <&pcie_phy 3>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie4: pcie at 48010000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x48010000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + brcm,pcie-ob; + ranges = <0x83000000 0x0 0x52000000 0x0 0x52000000 0 0x2000000>, + <0x43000000 0x6 0x00000000 0x6 0x00000000 0 0x80000000>; + PCIE_DMA_RANGES; + phys = <&pcie_phy 4>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie5: pcie at 48014000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x48014000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + brcm,pcie-ob; + ranges = <0x83000000 0x0 0x54000000 0x0 0x54000000 0 0x2000000>, + <0x43000000 0x6 0x80000000 0x6 0x80000000 0 0x80000000>; + PCIE_DMA_RANGES; + phys = <&pcie_phy 5>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie6: pcie at 48018000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x48018000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + brcm,pcie-ob; + ranges = <0x83000000 0x0 0x5a000000 0x0 0x5a000000 0 0x2000000>, + <0x43000000 0x7 0x00000000 0x7 0x00000000 0 0x80000000>; + PCIE_DMA_RANGES; + phys = <&pcie_phy 6>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie7: pcie at 4801c000 { + compatible = "brcm,iproc-pcie-paxb-v2"; + reg = <0 0x4801c000 0 0x4000>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + brcm,pcie-ob; + ranges = <0x83000000 0x0 0x5c000000 0x0 0x5c000000 0 0x2000000>, + <0x43000000 0x8 0x00000000 0x8 0x00000000 0 0x80000000>; + PCIE_DMA_RANGES; + phys = <&pcie_phy 7>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie8: pcie at 60400000 { + compatible = "brcm,iproc-pcie-paxc-v2"; + reg = <0 0x60400000 0 0x1000>; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>; + status = "disabled"; + pci at 0,0 { + compatible = "pci-bridge"; + reg = <0x0000 0 0 0 0>; + }; + }; + + pcie_phy: phy at 0 { + compatible = "brcm,sr-pcie-phy"; + reg = <0 0x40000000 0 0x200>, + <0 0x6641d000 0 0x100>; + reg-names = "reg_base", "cdru_base"; + #address-cells = <3>; + #size-cells = <2>; + #phy-cells = <1>; + }; };

[v1,16/49] arm: dts: ns3: add PAXB PCIe host and phy node

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