@@ -699,6 +699,15 @@ config TARGET_BCMNS2
ARMv8 Cortex-A57 processors targeting a broad range of networking
applications.
+config TARGET_BCMNS3
+ bool "Support Broadcom NS3"
+ select ARM64
+ select BOARD_LATE_INIT
+ help
+ Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
+ ARMv8 Cortex-A72 processors targeting a broad range of networking
+ applications.
+
config ARCH_EXYNOS
bool "Samsung EXYNOS"
select DM
@@ -1834,6 +1843,7 @@ source "board/broadcom/bcm968580xref/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
source "board/broadcom/bcmns2/Kconfig"
+source "board/broadcom/bcmns3/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/eets/pdu001/Kconfig"
@@ -885,6 +885,8 @@ dtb-$(CONFIG_ARCH_BCM68360) += \
dtb-$(CONFIG_ARCH_BCM6858) += \
bcm968580xref.dtb
+dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
+
dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
new file mode 100644
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Broadcom
+ */
+
+/dts-v1/;
+
+#include "ns3.dtsi"
+
+/ {
+ model = "NS3 model";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
new file mode 100644
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Broadcom
+ */
+
+#include "skeleton64.dtsi"
+
+/ {
+ compatible = "brcm,ns3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>,
+ <0x8 0x80000000 0x1 0x80000000>;
+ };
+
+ hsls {
+ compatible = "simple-bus";
+ dma-ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x68900000 0x17700000>;
+
+ uart1: uart at 110000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00110000 0x1000>;
+ reg-shift = <2>;
+ clock-frequency = <25000000>;
+ status = "disabled";
+ };
+ };
+};
new file mode 100644
@@ -0,0 +1,15 @@
+if TARGET_BCMNS3
+
+config SYS_BOARD
+ default "bcmns3"
+
+config SYS_VENDOR
+ default "broadcom"
+
+config SYS_SOC
+ default "bcmns3"
+
+config SYS_CONFIG_NAME
+ default "bcm_ns3"
+
+endif
new file mode 100644
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 Broadcom.
+
+obj-y := ns3.o
new file mode 100644
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Broadcom.
+ *
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <asm/system.h>
+#include <fdtdec.h>
+
+static struct mm_region ns3_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = ns3_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_mem_size_base() != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
new file mode 100644
@@ -0,0 +1,20 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BCMNS3=y
+CONFIG_SYS_TEXT_BASE=0xFF000000
+CONFIG_ENV_SIZE=0x80000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_LOGLEVEL=7
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SILENT_U_BOOT_ONLY=y
+# CONFIG_SILENT_CONSOLE_UPDATE_ON_SET is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot> "
+CONFIG_SYS_XTRACE="n"
+# CONFIG_CMD_SOURCE is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="ns3-board"
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
new file mode 100644
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom.
+ *
+ */
+
+#ifndef __BCM_NS3_H
+#define __BCM_NS3_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_HOSTNAME "NS3"
+
+/* Physical Memory Map */
+#define V2M_BASE 0x80000000
+#define PHYS_SDRAM_1 V2M_BASE
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x80000)
+
+/*
+ * Initial SP before reloaction is placed at end of first DRAM bank,
+ * which is 0x1_0000_0000.
+ * Just before re-loaction, new SP is updated and re-location happens.
+ * So pointing the initial SP to end of 2GB DDR is not a problem
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x80000000)
+/* 12MB Malloc size */
+#define CONFIG_SYS_MALLOC_LEN (SZ_8M + SZ_4M)
+
+/* console configuration */
+#define CONFIG_SYS_NS16550_CLK 25000000
+
+#define CONFIG_SYS_CBSIZE SZ_1K
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#endif /* __BCM_NS3_H */
Add support for Broadcom Northstar 3 SoC. NS3 is a octo-core 64-bit ARMv8 Cortex-A72 processors targeting a broad range of networking applications. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com> --- arch/arm/Kconfig | 10 ++++++ arch/arm/dts/Makefile | 2 ++ arch/arm/dts/ns3-board.dts | 24 +++++++++++++ arch/arm/dts/ns3.dtsi | 34 ++++++++++++++++++ board/broadcom/bcmns3/Kconfig | 15 ++++++++ board/broadcom/bcmns3/Makefile | 5 +++ board/broadcom/bcmns3/ns3.c | 65 ++++++++++++++++++++++++++++++++++ configs/bcm_ns3_defconfig | 20 +++++++++++ include/configs/bcm_ns3.h | 40 +++++++++++++++++++++ 9 files changed, 215 insertions(+) create mode 100644 arch/arm/dts/ns3-board.dts create mode 100644 arch/arm/dts/ns3.dtsi create mode 100644 board/broadcom/bcmns3/Kconfig create mode 100644 board/broadcom/bcmns3/Makefile create mode 100644 board/broadcom/bcmns3/ns3.c create mode 100644 configs/bcm_ns3_defconfig create mode 100644 include/configs/bcm_ns3.h