Message ID | 20200424202335.v3.2.Ib571c64a8c50fcbe386e728e38bbd320427e4efb@changeid |
---|---|
State | Superseded |
Headers | show |
Series | arm: stm32mp1: activate data cache in SPL and before relocation | expand |
Hi One typo below On 4/24/20 8:24 PM, Patrick Delaunay wrote: > Activate cache on DDR to improves the accesses to DDR used by SPL: s/improves/improve > - CONFIG_SPL_BSS_START_ADDR > - CONFIG_SYS_SPL_MALLOC_START > > Cache is configured only when DDR is fully initialized, > to avoid speculative access and issue in get_ram_size(). > Data cache is deactivated at the end of SPL, to flush the data cache > and the TLB. > > Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com> > --- > > Changes in v3: > - remove debug message "bye" > > Changes in v2: > - new > > arch/arm/mach-stm32mp/spl.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c > index f85391c6af..e50a21c3b7 100644 > --- a/arch/arm/mach-stm32mp/spl.c > +++ b/arch/arm/mach-stm32mp/spl.c > @@ -4,6 +4,7 @@ > */ > > #include <common.h> > +#include <cpu_func.h> > #include <dm.h> > #include <hang.h> > #include <spl.h> > @@ -115,4 +116,22 @@ void board_init_f(ulong dummy) > printf("DRAM init failed: %d\n", ret); > hang(); > } > + > + /* > + * activate cache on DDR only when DDR is fully initialized > + * to avoid speculative access and issue in get_ram_size() > + */ > + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) > + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, > + DCACHE_DEFAULT_OPTION); > +} > + > +void spl_board_prepare_for_boot(void) > +{ > + dcache_disable(); > +} > + > +void spl_board_prepare_for_boot_linux(void) > +{ > + dcache_disable(); > } Reviewed-by: Patrice Chotard <patrice.chotard at st.com> Thanks
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index f85391c6af..e50a21c3b7 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <cpu_func.h> #include <dm.h> #include <hang.h> #include <spl.h> @@ -115,4 +116,22 @@ void board_init_f(ulong dummy) printf("DRAM init failed: %d\n", ret); hang(); } + + /* + * activate cache on DDR only when DDR is fully initialized + * to avoid speculative access and issue in get_ram_size() + */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, + DCACHE_DEFAULT_OPTION); +} + +void spl_board_prepare_for_boot(void) +{ + dcache_disable(); +} + +void spl_board_prepare_for_boot_linux(void) +{ + dcache_disable(); }
Activate cache on DDR to improves the accesses to DDR used by SPL: - CONFIG_SPL_BSS_START_ADDR - CONFIG_SYS_SPL_MALLOC_START Cache is configured only when DDR is fully initialized, to avoid speculative access and issue in get_ram_size(). Data cache is deactivated at the end of SPL, to flush the data cache and the TLB. Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com> --- Changes in v3: - remove debug message "bye" Changes in v2: - new arch/arm/mach-stm32mp/spl.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)