@@ -36,6 +36,7 @@ config BCM2711_32B
select BCM2711
select ARMV7_LPAE
select CPU_V7A
+ select PHYS_64BIT
config BCM2711_64B
bool "Broadcom BCM2711 SoC 64-bit support"
@@ -6,6 +6,13 @@
#ifndef _BCM283x_BASE_H_
#define _BCM283x_BASE_H_
+#include <linux/types.h>
+
extern unsigned long rpi_bcm283x_base;
+#ifdef CONFIG_ARMV7_LPAE
+extern void *rpi4_phys_to_virt(phys_addr_t paddr);
+#define phys_to_virt(x) rpi4_phys_to_virt(x)
+#endif
+
#endif
@@ -145,6 +145,58 @@ int mach_cpu_init(void)
}
#ifdef CONFIG_ARMV7_LPAE
+
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
+
+void *rpi4_phys_to_virt(phys_addr_t paddr)
+{
+ if (paddr >= BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS)
+ paddr = paddr - BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS +
+ BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT;
+ return (void *)(unsigned long)paddr;
+}
+
+static void set_section_phys(unsigned int section, phys_addr_t phys,
+ enum dcache_option option)
+{
+ u64 *page_table = (u64 *)gd->arch.tlb_addr;
+ /* Need to set the access flag to not fault */
+ u64 value = TTB_SECT_AP | TTB_SECT_AF;
+
+ /* Add the page offset */
+ value |= (phys);
+
+ /* Add caching bits */
+ value |= option;
+
+ /* Set PTE */
+ page_table[section] = value;
+}
+
+static void rpi4_create_pcie_xhci_mapping(void)
+{
+ unsigned sect = BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT >> MMU_SECTION_SHIFT;
+ phys_addr_t phys_addr = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS;
+ unsigned int size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE;
+
+ while (size) {
+ set_section_phys(sect, phys_addr, DCACHE_OFF);
+ sect++;
+ phys_addr += MMU_SECTION_SIZE;
+ size -= MMU_SECTION_SIZE;
+ }
+}
+
+void arm_init_domains(void)
+{
+ /*
+ * Hijack this function to prepare a mappings for the PCIe MMIO
+ * region for the XHCI controller on RPi4 board.
+ * This code is called before enabling the MMU in ARM 32bit mode.
+ */
+ rpi4_create_pcie_xhci_mapping();
+}
+
void enable_caches(void)
{
dcache_enable();