| Message ID | 20200421165059.19394-8-s.nawrocki@samsung.com |
|---|---|
| State | New |
| Headers | show |
| Series | USB host support for Raspberry Pi 4 board | expand |
Hi Sylwester, On Wed, Apr 22, 2020 at 12:51 AM Sylwester Nawrocki <s.nawrocki at samsung.com> wrote: > > Add PCI Express capability definitions required by the Broadcom STB PCIe > driver. > > Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com> > --- > include/pci.h | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/include/pci.h b/include/pci.h > index 3d7646d..2b25a17 100644 > --- a/include/pci.h > +++ b/include/pci.h > @@ -481,10 +481,17 @@ > #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ > > #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ > +#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ > +#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ > #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ > > #define PCI_EXP_LNKSTA 18 /* Link Status */ > +#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ > +#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ > +#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ > + > #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ > +#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ Please put PCI_EXP_LNKCTL2 after PCI_EXP_SLTCAP (sorted in order) > > #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ > #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ > -- Other than that, Reviewed-by: Bin Meng <bmeng.cn at gmail.com> Regards, Bin
On 22.04.2020 08:16, Bin Meng wrote: > On Wed, Apr 22, 2020 at 12:51 AM Sylwester Nawrocki > <s.nawrocki at samsung.com> wrote: >> #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ >> +#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ >> +#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ >> #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ >> >> #define PCI_EXP_LNKSTA 18 /* Link Status */ >> +#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ >> +#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ >> +#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ >> + >> #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ >> +#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ > > Please put PCI_EXP_LNKCTL2 after PCI_EXP_SLTCAP (sorted in order) Thanks for pointing this out, will be corrected in next iteration. >> #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ >> #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ -- Regards, Sylwester
diff --git a/include/pci.h b/include/pci.h index 3d7646d..2b25a17 100644 --- a/include/pci.h +++ b/include/pci.h @@ -481,10 +481,17 @@ #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ +#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ +#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ +#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ + #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
Add PCI Express capability definitions required by the Broadcom STB PCIe driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com> --- include/pci.h | 7 +++++++ 1 file changed, 7 insertions(+)