| Message ID | 20200421165059.19394-5-s.nawrocki@samsung.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | USB host support for Raspberry Pi 4 board | expand |
Hi Sylwester, On Tue, 2020-04-21 at 18:50 +0200, Sylwester Nawrocki wrote: > From: Marek Szyprowski <m.szyprowski at samsung.com> > > Create a non-cacheable mapping for the 0x600000000 physical memory region, > where MMIO registers for the PCIe XHCI controller are instantiated by the > PCIe bridge. > > Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com> > --- > arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c > index 4295356..6a748da 100644 > --- a/arch/arm/mach-bcm283x/init.c > +++ b/arch/arm/mach-bcm283x/init.c > @@ -11,10 +11,15 @@ > #include <dm/device.h> > #include <fdt_support.h> > > +#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL > +#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL Where did you got this size from? I read from the Linux device tree the following: pcie0: pcie at 7d500000 { compatible = "brcm,bcm2711-pcie"; [...] ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; [...] }; Shouldn't the size be 0x4000000 then? Other than that the patch looks good to me. Regards, Nicolas -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: This is a digitally signed message part URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200422/f49ed794/attachment.sig>
Hi Nicolas, On 22.04.2020 11:46, Nicolas Saenz Julienne wrote: > On Tue, 2020-04-21 at 18:50 +0200, Sylwester Nawrocki wrote: >> From: Marek Szyprowski <m.szyprowski at samsung.com> >> >> Create a non-cacheable mapping for the 0x600000000 physical memory region, >> where MMIO registers for the PCIe XHCI controller are instantiated by the >> PCIe bridge. >> >> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com> >> --- >> arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++--- >> 1 file changed, 15 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c >> index 4295356..6a748da 100644 >> --- a/arch/arm/mach-bcm283x/init.c >> +++ b/arch/arm/mach-bcm283x/init.c >> @@ -11,10 +11,15 @@ >> #include <dm/device.h> >> #include <fdt_support.h> >> >> +#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL >> +#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL > Where did you got this size from? I read from the Linux device tree the > following: > > pcie0: pcie at 7d500000 { > compatible = "brcm,bcm2711-pcie"; > [...] > ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 > 0x0 0x04000000>; > [...] > }; > > Shouldn't the size be 0x4000000 then? > > Other than that the patch looks good to me. Well, I reduced the window to 0x800000 to make it fit somewhere nicely in the 32bit address space. We can limit it even to a single section (2MiB), that's more than needed by the XHCI controller anyway. I can add a comment about that. Best regards
On Wed, 2020-04-22 at 11:54 +0200, Marek Szyprowski wrote: > Hi Nicolas, > > On 22.04.2020 11:46, Nicolas Saenz Julienne wrote: > > On Tue, 2020-04-21 at 18:50 +0200, Sylwester Nawrocki wrote: > > > From: Marek Szyprowski <m.szyprowski at samsung.com> > > > > > > Create a non-cacheable mapping for the 0x600000000 physical memory region, > > > where MMIO registers for the PCIe XHCI controller are instantiated by the > > > PCIe bridge. > > > > > > Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com> > > > --- > > > arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++--- > > > 1 file changed, 15 insertions(+), 3 deletions(-) > > > > > > diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c > > > index 4295356..6a748da 100644 > > > --- a/arch/arm/mach-bcm283x/init.c > > > +++ b/arch/arm/mach-bcm283x/init.c > > > @@ -11,10 +11,15 @@ > > > #include <dm/device.h> > > > #include <fdt_support.h> > > > > > > +#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL > > > +#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL > > Where did you got this size from? I read from the Linux device tree the > > following: > > > > pcie0: pcie at 7d500000 { > > compatible = "brcm,bcm2711-pcie"; > > [...] > > ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 > > 0x0 0x04000000>; > > [...] > > }; > > > > Shouldn't the size be 0x4000000 then? > > > > Other than that the patch looks good to me. > > Well, I reduced the window to 0x800000 to make it fit somewhere nicely > in the 32bit address space. We can limit it even to a single section > (2MiB), that's more than needed by the XHCI controller anyway. I can add > a comment about that. Fair enough. Thanks, Nicolas -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: This is a digitally signed message part URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200422/f26dc25b/attachment.sig>
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 4295356..6a748da 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -11,10 +11,15 @@ #include <dm/device.h> #include <fdt_support.h> +#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL +#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL + #ifdef CONFIG_ARM64 #include <asm/armv8/mmu.h> -static struct mm_region bcm283x_mem_map[] = { +#define MAX_MAP_MAX_ENTRIES (4) + +static struct mm_region bcm283x_mem_map[MAX_MAP_MAX_ENTRIES] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, @@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = { } }; -static struct mm_region bcm2711_mem_map[] = { +static struct mm_region bcm2711_mem_map[MAX_MAP_MAX_ENTRIES] = { { .virt = 0x00000000UL, .phys = 0x00000000UL, @@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { + .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { /* List terminator */ 0, } @@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) { int i; - for (i = 0; i < 2; i++) { + for (i = 0; i < MAX_MAP_MAX_ENTRIES; i++) { mem_map[i].virt = pd[i].virt; mem_map[i].phys = pd[i].phys; mem_map[i].size = pd[i].size;