| Message ID | 20200420100607.23009-1-jagan@amarulasolutions.com |
|---|---|
| State | Accepted |
| Commit | 5bf3f3dd11db4048d7ad60f2ee210dc50da26051 |
| Headers | show |
| Series | [1/2] mtd: spi-nor: Enable QE bit for ISSI flash | expand |
Hi Jagan, > -----Original Message----- > From: Jagan Teki <jagan at amarulasolutions.com> > Sent: Monday, April 20, 2020 3:36 PM > To: Vignesh R <vigneshr at ti.com>; u-boot at lists.denx.de > Cc: Bin Meng <bmeng.cn at gmail.com>; linux- > amarula at amarulasolutions.com; Jagan Teki > <jagan at amarulasolutions.com>; Sagar Kadam <sagar.kadam at sifive.com> > Subject: [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > Enable QE bit for ISSI flash chips. > > QE enablement logic is similar to what Micromax has, so reuse the existing > code itself. nits: s/Micromax/Macronix Thanks, Sagar Kadam > > Cc: Sagar Shrikant Kadam <sagar.kadam at sifive.com> > Signed-off-by: Jagan Teki <jagan at amarulasolutions.com> > --- > drivers/mtd/spi/spi-nor-core.c | 1 + > include/linux/mtd/spi-nor.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c > index 7b6ad495ac..e0f6e4d6c3 100644 > --- a/drivers/mtd/spi/spi-nor-core.c > +++ b/drivers/mtd/spi/spi-nor-core.c > @@ -325,6 +325,7 @@ static int set_4byte(struct spi_nor *nor, const struct > flash_info *info, > case SNOR_MFR_MICRON: > /* Some Micron need WREN command; all will accept it */ > need_wren = true; > + case SNOR_MFR_ISSI: > case SNOR_MFR_MACRONIX: > case SNOR_MFR_WINBOND: > if (need_wren) > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index > ec144a08d8..233fdc341a 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -22,6 +22,7 @@ > #define SNOR_MFR_INTEL CFI_MFR_INTEL > #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */ > #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> > Micron */ > +#define SNOR_MFR_ISSI CFI_MFR_PMC > #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX > #define SNOR_MFR_SPANSION CFI_MFR_AMD > #define SNOR_MFR_SST CFI_MFR_SST > -- > 2.17.1
On Mon, Apr 20, 2020 at 9:56 PM Sagar Kadam <sagar.kadam at sifive.com> wrote: > > Hi Jagan, > > > -----Original Message----- > > From: Jagan Teki <jagan at amarulasolutions.com> > > Sent: Monday, April 20, 2020 3:36 PM > > To: Vignesh R <vigneshr at ti.com>; u-boot at lists.denx.de > > Cc: Bin Meng <bmeng.cn at gmail.com>; linux- > > amarula at amarulasolutions.com; Jagan Teki > > <jagan at amarulasolutions.com>; Sagar Kadam <sagar.kadam at sifive.com> > > Subject: [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash > > > > [External Email] Do not click links or attachments unless you recognize the > > sender and know the content is safe > > > > Enable QE bit for ISSI flash chips. > > > > QE enablement logic is similar to what Micromax has, so reuse the existing > > code itself. > > nits: s/Micromax/Macronix Will update while applying, thanks.
Hi Jagan, > -----Original Message----- > From: Jagan Teki <jagan at amarulasolutions.com> > Sent: Monday, April 20, 2020 9:58 PM > To: Sagar Kadam <sagar.kadam at sifive.com> > Cc: Vignesh R <vigneshr at ti.com>; u-boot at lists.denx.de; Bin Meng > <bmeng.cn at gmail.com>; linux-amarula at amarulasolutions.com > Subject: Re: [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Mon, Apr 20, 2020 at 9:56 PM Sagar Kadam <sagar.kadam at sifive.com> > wrote: > > > > Hi Jagan, > > > > > -----Original Message----- > > > From: Jagan Teki <jagan at amarulasolutions.com> > > > Sent: Monday, April 20, 2020 3:36 PM > > > To: Vignesh R <vigneshr at ti.com>; u-boot at lists.denx.de > > > Cc: Bin Meng <bmeng.cn at gmail.com>; linux- > > > amarula at amarulasolutions.com; Jagan Teki > > > <jagan at amarulasolutions.com>; Sagar Kadam > <sagar.kadam at sifive.com> > > > Subject: [PATCH 1/2] mtd: spi-nor: Enable QE bit for ISSI flash > > > > > > [External Email] Do not click links or attachments unless you > > > recognize the sender and know the content is safe > > > > > > Enable QE bit for ISSI flash chips. > > > > > > QE enablement logic is similar to what Micromax has, so reuse the > > > existing code itself. > > > > nits: s/Micromax/Macronix > > Will update while applying, thanks. Sure, no issues. Thanks & BR, Sagar Kadam
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 7b6ad495ac..e0f6e4d6c3 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -325,6 +325,7 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info, case SNOR_MFR_MICRON: /* Some Micron need WREN command; all will accept it */ need_wren = true; + case SNOR_MFR_ISSI: case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: if (need_wren) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index ec144a08d8..233fdc341a 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -22,6 +22,7 @@ #define SNOR_MFR_INTEL CFI_MFR_INTEL #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */ #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */ +#define SNOR_MFR_ISSI CFI_MFR_PMC #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST
Enable QE bit for ISSI flash chips. QE enablement logic is similar to what Micromax has, so reuse the existing code itself. Cc: Sagar Shrikant Kadam <sagar.kadam at sifive.com> Signed-off-by: Jagan Teki <jagan at amarulasolutions.com> --- drivers/mtd/spi/spi-nor-core.c | 1 + include/linux/mtd/spi-nor.h | 1 + 2 files changed, 2 insertions(+)