diff mbox series

net: phy: dp83867: Add SGMII mode type switching

Message ID e2272183564e38ea3d039dbc45ba945c5c973c4c.1582030255.git.michal.simek@xilinx.com
State Accepted
Commit a7844953acc9711f71bc864f69f922e87ff2ee9f
Headers show
Series net: phy: dp83867: Add SGMII mode type switching | expand

Commit Message

Michal Simek Feb. 18, 2020, 12:51 p.m. UTC 
This patch adds ability to switch beetween two PHY SGMII modes.
Some hardware, for example, FPGA IP designs may use 6-wire mode
which enables differential SGMII clock to MAC.

Patch description, dt flags have been done in mainline Linux by
commit a2111c460c0c ("net: phy: dp83867: Add documentation for SGMII mode type")
and by commit 507ddd5c0d47 ("net: phy: dp83867: Add SGMII mode type switching")

Signed-off-by: Michal Simek <michal.simek at xilinx.com>
---

 drivers/net/phy/dp83867.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Joe Hershberger March 5, 2020, 11:32 p.m. UTC | #1 
On Tue, Feb 18, 2020 at 6:51 AM Michal Simek <michal.simek at xilinx.com> wrote:
>
> This patch adds ability to switch beetween two PHY SGMII modes.
> Some hardware, for example, FPGA IP designs may use 6-wire mode
> which enables differential SGMII clock to MAC.
>
> Patch description, dt flags have been done in mainline Linux by
> commit a2111c460c0c ("net: phy: dp83867: Add documentation for SGMII mode type")
> and by commit 507ddd5c0d47 ("net: phy: dp83867: Add SGMII mode type switching")
>
> Signed-off-by: Michal Simek <michal.simek at xilinx.com>

Acked-by: Joe Hershberger <joe.hershberger at ni.com>
diff mbox series

Patch

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index e2ccbfd26887..b557f2496751 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -29,6 +29,7 @@ 
 #define DP83867_STRAP_STS2	0x006f
 #define DP83867_RGMIIDCTL	0x0086
 #define DP83867_IO_MUX_CFG	0x0170
+#define DP83867_SGMIICTL	0x00D3
 
 #define DP83867_SW_RESET	BIT(15)
 #define DP83867_SW_RESTART	BIT(14)
@@ -101,6 +102,9 @@ 
 /* CFG4 bits */
 #define DP83867_CFG4_PORT_MIRROR_EN		BIT(0)
 
+/* SGMIICTL bits */
+#define DP83867_SGMII_TYPE			BIT(14)
+
 enum {
 	DP83867_PORT_MIRRORING_KEEP,
 	DP83867_PORT_MIRRORING_EN,
@@ -116,6 +120,7 @@  struct dp83867_private {
 	int port_mirroring;
 	bool set_clk_output;
 	unsigned int clk_output_sel;
+	bool sgmii_ref_clk_en;
 };
 
 static int dp83867_config_port_mirroring(struct phy_device *phydev)
@@ -236,6 +241,9 @@  static int dp83867_of_init(struct phy_device *phydev)
 	if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
 		dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
 
+	if (ofnode_read_bool(node, "ti,sgmii-ref-clock-output-enable"))
+		dp83867->sgmii_ref_clk_en = true;
+
 	return 0;
 }
 #else
@@ -329,6 +337,10 @@  static int dp83867_config(struct phy_device *phydev)
 		phy_write_mmd(phydev, DP83867_DEVADDR,
 			      DP83867_RGMIIDCTL, delay);
 	} else if (phy_interface_is_sgmii(phydev)) {
+		if (dp83867->sgmii_ref_clk_en)
+			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL,
+				      DP83867_SGMII_TYPE);
+
 		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 			  (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));