| Message ID | 20200214091820.28877-6-t-kristo@ti.com |
|---|---|
| State | New |
| Headers | show |
| Series | ESM support for TI K3 SoCs | expand |
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi new file mode 100644 index 0000000000..c6c60b44ec --- /dev/null +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ + +&tps659413a { + esm: esm { + compatible = "ti,tps659413-esm"; + u-boot,dm-spl; + }; +};
The ESM handling on J7 processor board requires routing the MCU_SAFETY_ERROR signal to the PMIC on the board for critical safety error handling. The PMIC itself should then reset the board based on receiving it. Enable the support for the board by adding the esm node in place. Signed-off-by: Tero Kristo <t-kristo at ti.com> --- .../arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi