diff mbox

xen: arm: Fixing ttbcr (TCR_EL1 for AArch64) size.

Message ID 1386072224-4478-1-git-send-email-pranavkumar@linaro.org
State New
Headers show

Commit Message

PranavkumarSawargaonkar Dec. 3, 2013, 12:03 p.m. UTC 
This patch fixes size of ttbcr register (TCR_EL1 in case of AArch64)
and it's programming considering size in case of context switch.

Currently ttbcr is defined as 32b register but for AArch64 TCR_EL1
size is 64b.

Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
---
 xen/arch/arm/domain.c        |    8 ++++++++
 xen/include/asm-arm/domain.h |    4 ++++
 2 files changed, 12 insertions(+)

Comments

Ian Campbell Dec. 3, 2013, 1:47 p.m. UTC | #1 
On Tue, 2013-12-03 at 17:33 +0530, Pranavkumar Sawargaonkar wrote:
> This patch fixes size of ttbcr register (TCR_EL1 in case of AArch64)
> and it's programming considering size in case of context switch.
> 
> Currently ttbcr is defined as 32b register but for AArch64 TCR_EL1
> size is 64b.

Thanks for tracking this down.

> Signed-off-by: Anup Patel <anup.patel@linaro.org>
> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
[...]
> diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
> index d5cae2e..2aa4443 100644
> --- a/xen/include/asm-arm/domain.h
> +++ b/xen/include/asm-arm/domain.h
> @@ -165,7 +165,11 @@ struct arch_vcpu
>  
>      /* MMU */
>      register_t vbar;
> +#ifdef CONFIG_ARM_32
>      uint32_t ttbcr;
> +#else
> +    uint64_t ttbcr;
> +#endif

I think that actually only this hunk is required. 

Actually, the correct type to use is register_t (which is defined to be
the "native" register size, 32- or 64-bit as appropriate). That avoids
the ifdef.

The READ/WRITE_SYSREG macros are also defined to deal in the "native"
bit width so the other hunks are unnecessary.

The SYSREG32/64 variants are for use with a register which is a fixed
width independent of the platform.

Thanks,
Ian.
diff mbox

Patch

diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 52d2403..74ab046 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -89,7 +89,11 @@  static void ctxt_switch_from(struct vcpu *p)
 
     /* MMU */
     p->arch.vbar = READ_SYSREG(VBAR_EL1);
+#ifdef CONFIG_ARM_32
     p->arch.ttbcr = READ_SYSREG(TCR_EL1);
+#else
+    p->arch.ttbcr = READ_SYSREG64(TCR_EL1);
+#endif
     p->arch.ttbr0 = READ_SYSREG64(TTBR0_EL1);
     p->arch.ttbr1 = READ_SYSREG64(TTBR1_EL1);
     if ( is_pv32_domain(p->domain) )
@@ -168,7 +172,11 @@  static void ctxt_switch_to(struct vcpu *n)
 
     /* MMU */
     WRITE_SYSREG(n->arch.vbar, VBAR_EL1);
+#if defined(CONFIG_ARM_32)
     WRITE_SYSREG(n->arch.ttbcr, TCR_EL1);
+#else
+    WRITE_SYSREG64(n->arch.ttbcr, TCR_EL1);
+#endif
     WRITE_SYSREG64(n->arch.ttbr0, TTBR0_EL1);
     WRITE_SYSREG64(n->arch.ttbr1, TTBR1_EL1);
     if ( is_pv32_domain(n->domain) )
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index d5cae2e..2aa4443 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -165,7 +165,11 @@  struct arch_vcpu
 
     /* MMU */
     register_t vbar;
+#ifdef CONFIG_ARM_32
     uint32_t ttbcr;
+#else
+    uint64_t ttbcr;
+#endif
     uint64_t ttbr0, ttbr1;
 
     uint32_t dacr; /* 32-bit guests only */