| Message ID | 20200512204543.22090-4-robh@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | [1/5] spi: dt-bindings: sifive: Add missing 2nd register region | expand |
diff --git a/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml b/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml index b503b1a918a5..4d13e6bc1c50 100644 --- a/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml @@ -25,6 +25,12 @@ properties: power-domains: maxItems: 1 + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + "#address-cells": const: 2 @@ -47,6 +53,8 @@ patternProperties: Documentation/devicetree/bindings/ufs/cdns,ufshc.txt for binding documentation of child node +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h>
The ti,j721e-ufs schema is missing an 'additionalProperties: false'. Add that and and the missing assigned-clock properties. Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml | 8 ++++++++ 1 file changed, 8 insertions(+)