Message ID | 20200317093922.20785-18-lkundrak@v3.sk |
---|---|
State | New |
Headers | show |
Series | DT: Improve validation for Marvell SoCs | expand |
diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml index 8fded83c519ad..c9384ed685b8f 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -363,7 +363,7 @@ examples: keep-power-in-suspend; wakeup-source; mmc-pwrseq = <&sdhci0_pwrseq>; - clk-phase-sd-hs = <63>, <72>; + clk-phase-sd-hs = <63 72>; }; - |
This way the validator can know that the two cells constitute a singlej pair of clock phase degrees value, not separate items Otherwise it is unhappy: mmc-controller.example.dt.yaml: mmc@ab000000: clk-phase-sd-hs:0: [63] is too short mmc-controller.example.dt.yaml: mmc@ab000000: clk-phase-sd-hs:1: [72] is too short Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> --- Documentation/devicetree/bindings/mmc/mmc-controller.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)