Message ID | 1584985955-19101-9-git-send-email-skomatineni@nvidia.com |
---|---|
State | New |
Headers | show |
Series | [RFC,v5,1/9] arm64: tegra: Fix sor powergate clocks and reset | expand |
diff --git a/include/dt-bindings/reset/tegra210-car.h b/include/dt-bindings/reset/tegra210-car.h index 9dc84ec..8755946 100644 --- a/include/dt-bindings/reset/tegra210-car.h +++ b/include/dt-bindings/reset/tegra210-car.h @@ -10,5 +10,6 @@ #define TEGRA210_RESET(x) (7 * 32 + (x)) #define TEGRA210_RST_DFLL_DVCO TEGRA210_RESET(0) #define TEGRA210_RST_ADSP TEGRA210_RESET(1) +#define TEGRA210_RST_VI 20 #endif /* _DT_BINDINGS_RESET_TEGRA210_CAR_H */
This patch adds ID for Tegra210 VI controller reset to use with device tree. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- include/dt-bindings/reset/tegra210-car.h | 1 + 1 file changed, 1 insertion(+)