| Message ID | 1379510122-9467-3-git-send-email-julien.grall@linaro.org |
|---|---|
| State | Superseded, archived |
| Headers | show |
On Wed, 2013-09-18 at 14:15 +0100, Julien Grall wrote: > When Xen initialize the GIC distributor, we need to route all the IRQs to > the boot CPU. The CPU ID can differ between Xen and the GIC. > > When ITARGETSR0 is read, each field will return a value that corresponds > only to the processor reading the register. So Xen can use the PPI 0 to > initialize correctly the routing. > > Signed-off-by: Julien Grall <julien.grall@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com>
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 091eb36..b969d23 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -258,9 +258,10 @@ void gic_route_dt_irq(const struct dt_irq *irq, const cpumask_t *cpu_mask, static void __init gic_dist_init(void) { uint32_t type; - uint32_t cpumask = 1 << smp_processor_id(); + uint32_t cpumask; int i; + cpumask = GICD[GICD_ITARGETSR] & 0xff; cpumask |= cpumask << 8; cpumask |= cpumask << 16;
When Xen initialize the GIC distributor, we need to route all the IRQs to the boot CPU. The CPU ID can differ between Xen and the GIC. When ITARGETSR0 is read, each field will return a value that corresponds only to the processor reading the register. So Xen can use the PPI 0 to initialize correctly the routing. Signed-off-by: Julien Grall <julien.grall@linaro.org> --- xen/arch/arm/gic.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)