| Message ID | 20200226180901.89940-3-andre.przywara@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm: calxeda: update DTS, bindings and MAINTAINERS | expand |
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi index 66ee1d34f72b..f819e3328a9e 100644 --- a/arch/arm/boot/dts/ecx-common.dtsi +++ b/arch/arm/boot/dts/ecx-common.dtsi @@ -114,8 +114,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xfff36000 0x1000>; interrupts = <0 20 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; + clocks = <&pclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; smic@fff3a000 {
The PL011 UART binding requires two clocks to be named in a node. Add the second clock, which is the bus gate, that just gets enabled. Since this is a fixed clock anyway, it doesn't make any difference. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/boot/dts/ecx-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)