| Message ID | 20200227115526.28075-1-mans@mansr.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] ARM: dts: sunxi: h3/h5: add r_pwm node | expand |
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 107eeafad20a..54b32537d6ae 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -871,6 +871,21 @@ pins = "PL0", "PL1"; function = "s_i2c"; }; + + r_pwm_pin: r-pwm-pin { + pins = "PL10"; + function = "s_pwm"; + }; + }; + + r_pwm: pwm@1f03800 { + compatible = "allwinner,sun8i-h3-pwm"; + reg = <0x01f03800 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <&r_pwm_pin>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; }; }; };
There is a second PWM unit available in the PL I/O block. Add a node and pinmux definition for it. Signed-off-by: Mans Rullgard <mans@mansr.com> --- Changed in v2: - use singular name (pin vs pins) for pinmux group - set pinmux in device node as there is only one choice --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)