new file mode 100644
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
+
+/ {
+ cpu_opp_table: cpu-opp-table {
+ compatible = "allwinner,sun50i-h6-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;
+ opp-shared;
+
+ opp@480000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <480000000>;
+
+ opp-microvolt-speed0 = <1135000>;
+ opp-microvolt-speed1 = <1135000>;
+ opp-microvolt-speed2 = <1135000>;
+ };
+
+ opp@720000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <720000000>;
+
+ opp-microvolt-speed0 = <1135000>;
+ opp-microvolt-speed1 = <1135000>;
+ opp-microvolt-speed2 = <1135000>;
+ };
+
+ opp@816000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <816000000>;
+
+ opp-microvolt-speed0 = <1135000>;
+ opp-microvolt-speed1 = <1135000>;
+ opp-microvolt-speed2 = <1135000>;
+ };
+
+ opp@888000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <888000000>;
+
+ opp-microvolt-speed0 = <1135000>;
+ opp-microvolt-speed1 = <1135000>;
+ opp-microvolt-speed2 = <1135000>;
+ };
+
+ opp@1080000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1080000000>;
+
+ opp-microvolt-speed0 = <1135000>;
+ opp-microvolt-speed1 = <1135000>;
+ opp-microvolt-speed2 = <1135000>;
+ };
+
+ opp@1320000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1320000000>;
+
+ opp-microvolt-speed0 = <1135000>;
+ opp-microvolt-speed1 = <1135000>;
+ opp-microvolt-speed2 = <1135000>;
+ };
+
+ opp@1488000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1488000000>;
+
+ opp-microvolt-speed0 = <1135000>;
+ opp-microvolt-speed1 = <1135000>;
+ opp-microvolt-speed2 = <1135000>;
+ };
+
+ opp@1608000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1608000000>;
+
+ opp-microvolt-speed0 = <1135000>;
+ opp-microvolt-speed1 = <1135000>;
+ opp-microvolt-speed2 = <1135000>;
+ };
+
+ opp@1704000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1704000000>;
+
+ opp-microvolt-speed0 = <1135000>;
+ opp-microvolt-speed1 = <1135000>;
+ opp-microvolt-speed2 = <1135000>;
+ };
+
+ opp@1800000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1800000000>;
+
+ opp-microvolt-speed0 = <1135000>;
+ opp-microvolt-speed1 = <1135000>;
+ opp-microvolt-speed2 = <1135000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
@@ -4,7 +4,7 @@
/dts-v1/;
#include "sun50i-h6.dtsi"
-#include "sun50i-h6-cpu-opp.dtsi"
+#inlcude "sun50i-h6-tanix-tx6-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
Tanix TX6 has a fixed regulator. As DVFS is instructed to change voltage to meet OPP table. The DVFS is not working as expected. Introduce a dedicated OPP Table where voltage are equals to the fixed regulator. Reported-by: Piotr Oniszczuk <warpme@o2.pl> Fixes: add1e27fb703 ("arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6") Signed-off-by: Clément Péron <peron.clem@gmail.com> --- .../sun50i-h6-tanix-tx6-cpu-opp.dtsi | 116 ++++++++++++++++++ .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 2 +- 2 files changed, 117 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-cpu-opp.dtsi