diff mbox series

ARM: dts: prima: Align L2 cache-controller nodename with dtschema

Message ID 20200626080613.3955-1-krzk@kernel.org
State Accepted
Commit 53486d937cb5090eb6cabb4caf2b0e052136134d
Headers show
Series ARM: dts: prima: Align L2 cache-controller nodename with dtschema | expand

Commit Message

Krzysztof Kozlowski June 26, 2020, 8:06 a.m. UTC
Fix dtschema validator warnings like:
    l2-cache-controller@80040000: $nodename:0:
        'l2-cache-controller@80040000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/prima2.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Barry Song July 10, 2020, 5:50 a.m. UTC | #1
Krzysztof Kozlowski <krzk@kernel.org> 于2020年6月26日周五 下午8:06写道:
>

> Fix dtschema validator warnings like:

>     l2-cache-controller@80040000: $nodename:0:

>         'l2-cache-controller@80040000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

>

> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>


Acked-by: Barry Song <baohua@kernel.org>


> ---

>  arch/arm/boot/dts/prima2.dtsi | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

>

> diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi

> index 9c7b46b90c3c..7d3d93c22ed9 100644

> --- a/arch/arm/boot/dts/prima2.dtsi

> +++ b/arch/arm/boot/dts/prima2.dtsi

> @@ -50,7 +50,7 @@

>                 #size-cells = <1>;

>                 ranges = <0x40000000 0x40000000 0x80000000>;

>

> -               l2-cache-controller@80040000 {

> +               cache-controller@80040000 {

>                         compatible = "arm,pl310-cache";

>                         reg = <0x80040000 0x1000>;

>                         interrupts = <59>;

> --

> 2.17.1

>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 9c7b46b90c3c..7d3d93c22ed9 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -50,7 +50,7 @@ 
 		#size-cells = <1>;
 		ranges = <0x40000000 0x40000000 0x80000000>;
 
-		l2-cache-controller@80040000 {
+		cache-controller@80040000 {
 			compatible = "arm,pl310-cache";
 			reg = <0x80040000 0x1000>;
 			interrupts = <59>;