| Message ID | 20200627161957.134376-6-anup.patel@wdc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2,1/5] RISC-V: Add mechanism to provide custom IPI operations | expand |
On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote: > We add DT bindings documentation for CLINT device. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> > --- > .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++ > 1 file changed, 34 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt Bindings should be in DT schema format now. > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt > new file mode 100644 > index 000000000000..45b75347a7d5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt > @@ -0,0 +1,34 @@ > +SiFive Core Local Interruptor (CLINT) > +------------------------------------- > + > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts. > + > +It directly connects to the timer and inter-processor interrupt lines of > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt > +controller is the parent interrupt controller for CLINT device. > + > +The clock frequency of CLINT is specified via "timebase-frequency" DT > +property of "/cpus" DT node. The "timebase-frequency" DT property is > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml > + > +Required properties: > +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific A new versioning scheme from SiFive? To review, we don't do version numbers unless there's a well defined and documented scheme. IOW, one that's not s/w folks just making up v1, v2, v3, etc. > + string identifying the actual implementation can be added if implementation > + specific worked arounds are needed. > +- reg : Should contain 1 register range (address and length). > +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to > + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which > + has a riscv node as parent. > + > +Example: > + > + clint@2000000 { > + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint"; Doesn't match the binding. > + interrupts-extended = < > + &cpu1-intc 3 &cpu1-intc 7 > + &cpu2-intc 3 &cpu2-intc 7 > + &cpu3-intc 3 &cpu3-intc 7 > + &cpu4-intc 3 &cpu4-intc 7>; > + reg = <0x2000000 0x4000000>; > + }; > -- > 2.25.1 >
On Tue, Jul 14, 2020 at 8:07 AM Rob Herring <robh@kernel.org> wrote: > > On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote: > > We add DT bindings documentation for CLINT device. > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> > > --- > > .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++ > > 1 file changed, 34 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt > > Bindings should be in DT schema format now. Okay, will update. > > > > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt > > new file mode 100644 > > index 000000000000..45b75347a7d5 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt > > @@ -0,0 +1,34 @@ > > +SiFive Core Local Interruptor (CLINT) > > +------------------------------------- > > + > > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core > > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts. > > + > > +It directly connects to the timer and inter-processor interrupt lines of > > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt > > +controller is the parent interrupt controller for CLINT device. > > + > > +The clock frequency of CLINT is specified via "timebase-frequency" DT > > +property of "/cpus" DT node. The "timebase-frequency" DT property is > > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml > > + > > +Required properties: > > +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific > > A new versioning scheme from SiFive? To review, we don't do version > numbers unless there's a well defined and documented scheme. IOW, one > that's not s/w folks just making up v1, v2, v3, etc. The "riscv,clint0" is already used by various RISC-V systems (including QEMU). The "sifive,clint-1.0.0" is for being consistent with the PLIC versioning scheme. There is no clear documentation of CLINT versioning scheme. I think it's best to just drop "sifive,clint-1.0.0" . Agree ?? > > > + string identifying the actual implementation can be added if implementation > > + specific worked arounds are needed. > > +- reg : Should contain 1 register range (address and length). > > +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to > > + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which > > + has a riscv node as parent. > > + > > +Example: > > + > > + clint@2000000 { > > + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint"; > > Doesn't match the binding. Okay, will update. > > > + interrupts-extended = < > > + &cpu1-intc 3 &cpu1-intc 7 > > + &cpu2-intc 3 &cpu2-intc 7 > > + &cpu3-intc 3 &cpu3-intc 7 > > + &cpu4-intc 3 &cpu4-intc 7>; > > + reg = <0x2000000 0x4000000>; > > + }; > > -- > > 2.25.1 > > Regards, Anup
On Mon, Jul 13, 2020 at 9:47 PM Anup Patel <anup@brainfault.org> wrote: > > On Tue, Jul 14, 2020 at 8:07 AM Rob Herring <robh@kernel.org> wrote: > > > > On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote: > > > We add DT bindings documentation for CLINT device. > > > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> > > > --- > > > .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++ > > > 1 file changed, 34 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt > > > > Bindings should be in DT schema format now. > > Okay, will update. > > > > > > > > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt > > > new file mode 100644 > > > index 000000000000..45b75347a7d5 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt > > > @@ -0,0 +1,34 @@ > > > +SiFive Core Local Interruptor (CLINT) > > > +------------------------------------- > > > + > > > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core > > > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts. > > > + > > > +It directly connects to the timer and inter-processor interrupt lines of > > > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt > > > +controller is the parent interrupt controller for CLINT device. > > > + > > > +The clock frequency of CLINT is specified via "timebase-frequency" DT > > > +property of "/cpus" DT node. The "timebase-frequency" DT property is > > > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml > > > + > > > +Required properties: > > > +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific > > > > A new versioning scheme from SiFive? To review, we don't do version > > numbers unless there's a well defined and documented scheme. IOW, one > > that's not s/w folks just making up v1, v2, v3, etc. > > The "riscv,clint0" is already used by various RISC-V systems (including QEMU). Not my problem that undocumented bindings are being used. > The "sifive,clint-1.0.0" is for being consistent with the PLIC > versioning scheme. Where is that documented? This is what I expect you to be following or updating to match: Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt > > There is no clear documentation of CLINT versioning scheme. I think it's best > to just drop "sifive,clint-1.0.0" . Agree ?? No, because then you are left with a very generic compatible string. You need something specific enough to handle any implementation features/quirks/bugs without needing a DT update. Typically, this means a per SoC compatible string for a block as even the same IP version can have different integration quirks. Rob
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt new file mode 100644 index 000000000000..45b75347a7d5 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt @@ -0,0 +1,34 @@ +SiFive Core Local Interruptor (CLINT) +------------------------------------- + +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts. + +It directly connects to the timer and inter-processor interrupt lines of +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt +controller is the parent interrupt controller for CLINT device. + +The clock frequency of CLINT is specified via "timebase-frequency" DT +property of "/cpus" DT node. The "timebase-frequency" DT property is +described in: Documentation/devicetree/bindings/riscv/cpus.yaml + +Required properties: +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific + string identifying the actual implementation can be added if implementation + specific worked arounds are needed. +- reg : Should contain 1 register range (address and length). +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which + has a riscv node as parent. + +Example: + + clint@2000000 { + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint"; + interrupts-extended = < + &cpu1-intc 3 &cpu1-intc 7 + &cpu2-intc 3 &cpu2-intc 7 + &cpu3-intc 3 &cpu3-intc 7 + &cpu4-intc 3 &cpu4-intc 7>; + reg = <0x2000000 0x4000000>; + };