@@ -247,9 +247,15 @@ snd_pcm_uframes_t snd_dmaengine_pcm_pointer(struct snd_pcm_substream *substream)
status = dmaengine_tx_status(prtd->dma_chan, prtd->cookie, &state);
if (status == DMA_IN_PROGRESS || status == DMA_PAUSED) {
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ int sample_bits = snd_pcm_format_physical_width(runtime->format);
+
buf_size = snd_pcm_lib_buffer_bytes(substream);
if (state.residue > 0 && state.residue <= buf_size)
pos = buf_size - state.residue;
+
+ sample_bits *= runtime->channels;
+ runtime->delay = state.in_flight_bytes / (sample_bits / 8);
}
return bytes_to_frames(substream->runtime, pos);
@@ -1151,7 +1151,7 @@ static snd_pcm_uframes_t soc_pcm_pointer(struct snd_pcm_substream *substream)
}
delay += codec_delay;
- runtime->delay = delay;
+ runtime->delay += delay;
return offset;
}
Some DMA engines can have big FIFOs which adds to the latency. The DMAengine framework can report the FIFO utilization in bytes. Use this information for the delay reporting. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> --- Hi, 5.6-rc1 now have support for reporting the DMA cached data. With this patch we can include it to the delay calculation. The first DMA driver which reports this is the TI K3 UDMA driver. Regards, Peter sound/core/pcm_dmaengine.c | 6 ++++++ sound/soc/soc-pcm.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-)