@@ -20,6 +20,54 @@
interrupt-controller@2a40000 {
status = "okay";
};
+
+ ahub@2900800 {
+ status = "okay";
+
+ admaif@290f000 {
+ status = "okay";
+ };
+
+ i2s@2901000 {
+ status = "okay";
+ };
+
+ i2s@2901100 {
+ status = "okay";
+ };
+
+ i2s@2901200 {
+ status = "okay";
+ };
+
+ i2s@2901300 {
+ status = "okay";
+ };
+
+ i2s@2901400 {
+ status = "okay";
+ };
+
+ i2s@2901500 {
+ status = "okay";
+ };
+
+ dmic@2904000 {
+ status = "okay";
+ };
+
+ dmic@2904100 {
+ status = "okay";
+ };
+
+ dmic@2904200 {
+ status = "okay";
+ };
+
+ dspk@2905100 {
+ status = "okay";
+ };
+ };
};
i2c@3160000 {
@@ -21,6 +21,42 @@
interrupt-controller@2a40000 {
status = "okay";
};
+
+ ahub@2900800 {
+ status = "okay";
+
+ admaif@290f000 {
+ status = "okay";
+ };
+
+ i2s@2901000 {
+ status = "okay";
+ };
+
+ i2s@2901100 {
+ status = "okay";
+ };
+
+ i2s@2901300 {
+ status = "okay";
+ };
+
+ i2s@2901500 {
+ status = "okay";
+ };
+
+ dmic@2904100 {
+ status = "okay";
+ };
+
+ dmic@2904200 {
+ status = "okay";
+ };
+
+ dspk@2905000 {
+ status = "okay";
+ };
+ };
};
ddc: i2c@31c0000 {
@@ -118,12 +118,52 @@
aconnect@702c0000 {
status = "okay";
- dma@702e2000 {
+ dma-controller@702e2000 {
status = "okay";
};
interrupt-controller@702f9000 {
status = "okay";
};
+
+ ahub@702d0800 {
+ status = "okay";
+
+ admaif@702d0000 {
+ status = "okay";
+ };
+
+ i2s@702d1000 {
+ status = "okay";
+ };
+
+ i2s@702d1100 {
+ status = "okay";
+ };
+
+ i2s@702d1200 {
+ status = "okay";
+ };
+
+ i2s@702d1300 {
+ status = "okay";
+ };
+
+ i2s@702d1400 {
+ status = "okay";
+ };
+
+ dmic@702d4000 {
+ status = "okay";
+ };
+
+ dmic@702d4100 {
+ status = "okay";
+ };
+
+ dmic@702d4200 {
+ status = "okay";
+ };
+ };
};
};
@@ -806,4 +806,40 @@
vin-supply = <&avdd_1v05_pll>;
};
+
+ aconnect@702c0000 {
+ status = "okay";
+
+ dma-controller@702e2000 {
+ status = "okay";
+ };
+
+ interrupt-controller@702f9000 {
+ status = "okay";
+ };
+
+ ahub@702d0800 {
+ status = "okay";
+
+ admaif@702d0000 {
+ status = "okay";
+ };
+
+ i2s@702d1200 {
+ status = "okay";
+ };
+
+ i2s@702d1300 {
+ status = "okay";
+ };
+
+ dmic@702d4000 {
+ status = "okay";
+ };
+
+ dmic@702d4100 {
+ status = "okay";
+ };
+ };
+ };
};
This patch enables AHUB, ADMAIF modules for following Tegra platforms. Along with this specific instances of I/O modules are enabled as per the board design. * Jetson TX1 - I2S1, I2S2, I2S3, I2S4 and I2S5 - DMIC1, DMIC2 and DMIC3 * Jetson Nano - I2S3 and I2S4 - DMIC1 and DMIC2 * Jetson TX2 - I2S1, I2S2, I2S3, I2S4, I2S5 and I2S6 - DMIC1, DMIC2 and DMIC3 - DSPK2 * Jetson AGX Xavier - I2S1, I2S2, I2S4 and I2S6 - DMIC2 and DMIC3 - DSPK1 This helps to register above components with ASoC core. Signed-off-by: Sameer Pujar <spujar@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 48 ++++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 36 ++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 42 ++++++++++++++++++- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 36 ++++++++++++++++ 4 files changed, 161 insertions(+), 1 deletion(-)