| Message ID | 1588329036-18732-1-git-send-email-smasetty@codeaurora.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] arm64: dts: qcom: sc7180: Add A618 gpu dt blob | expand |
Hi, On Fri, May 1, 2020 at 3:30 AM Sharat Masetty <smasetty@codeaurora.org> wrote: > > This patch adds the required dt nodes and properties > to enabled A618 GPU. > > Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> > --- > * Remove GCC_DDRSS_GPU_AXI_CLK clock reference from gpu smmu node. > > arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++ > 1 file changed, 102 insertions(+) This is the newer version of the patch: https://lore.kernel.org/r/1581320465-15854-2-git-send-email-smasetty@codeaurora.org The change to remove the extra IOMMU clock matches our discussions and there's no longer anything blocking this from landing. Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org>
Hi, On Fri, May 1, 2020 at 3:30 AM Sharat Masetty <smasetty@codeaurora.org> wrote: > > This patch simply adds a new compatible string for SC7180 platform. > > Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> > --- > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 6515dbe..986098b 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -28,6 +28,7 @@ properties: > - enum: > - qcom,msm8996-smmu-v2 > - qcom,msm8998-smmu-v2 > + - qcom,sc7180-smmu-v2 > - qcom,sdm845-smmu-v2 > - const: qcom,smmu-v2 Is anything blocking this patch from landing now? -Doug
On Mon, May 18, 2020 at 01:59:49PM -0700, Doug Anderson wrote: > On Mon, May 18, 2020 at 7:39 AM Will Deacon <will@kernel.org> wrote: > > On Fri, May 15, 2020 at 12:05:39PM -0700, Doug Anderson wrote: > > > On Fri, May 1, 2020 at 3:30 AM Sharat Masetty <smasetty@codeaurora.org> wrote: > > > > > > > > This patch simply adds a new compatible string for SC7180 platform. > > > > > > > > Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> > > > > --- > > > > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + > > > > 1 file changed, 1 insertion(+) > > > > > > > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > > index 6515dbe..986098b 100644 > > > > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > > > > @@ -28,6 +28,7 @@ properties: > > > > - enum: > > > > - qcom,msm8996-smmu-v2 > > > > - qcom,msm8998-smmu-v2 > > > > + - qcom,sc7180-smmu-v2 > > > > - qcom,sdm845-smmu-v2 > > > > - const: qcom,smmu-v2 > > > > > > Is anything blocking this patch from landing now? > > > > I thought updates to the bindings usually went via Rob and the device-tree > > tree, but neither of those are on cc. > > > > Perhaps resend with that fixed? > > Ah, I guess I wasn't familiar with how things worked for this file, or > maybe things have changed recently? I'm used to most bindings going > through the same tree as the drivers that use them. Usually if things > are at all complicated maintainers wait for an Ack from Rob (so he > should have been CCed for sure) and then land. Just to clear this up: I'm happy to take DT stuff like this, but preferably with Rob's ack so that I know that (a) it's not a load of rubbish and (b) it probably won't conflict with his tree. So having the DT folks omitted from the CC list just rings alarm bells for me. > In this case it actually looks like Bjorn landed it in the Qualcomm > and I just didn't realize it. That seems like it should be fine since > it's in the middle of a clause that's all Qualcomm and the change > shouldn't be controversial in any way. :-) Ok! Will
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 4216b57..de9a054 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1373,6 +1373,108 @@ }; }; + gpu: gpu@5000000 { + compatible = "qcom,adreno-618.0", "qcom,adreno"; + #stream-id-cells = <16>; + reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, + <0 0x05061000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x05040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&gpucc CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; + reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; + power-domain-names = "cx", "gx"; + iommus = <&adreno_smmu 5>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,sc7180-gpucc"; reg = <0 0x05090000 0 0x9000>;
This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> --- * Remove GCC_DDRSS_GPU_AXI_CLK clock reference from gpu smmu node. arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) -- 1.9.1