| Message ID | 20200318011748.2104336-8-ehabkost@redhat.com |
|---|---|
| State | Accepted |
| Commit | 781c67ca5585b38a29076093ecdff4f273db5a35 |
| Headers | show |
| Series | None | expand |
On 3/18/20 2:17 AM, Eduardo Habkost wrote: > From: Peter Maydell <peter.maydell@linaro.org> > > The CPUClass has a 'reset' method. This is a legacy from when > TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any > more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()' > function is kept as the API which most places use to reset a CPU; it > is now a wrapper which calls device_cold_reset() and then the > tracepoint function. > > This change should not cause CPU objects to be reset more often > than they are at the moment, because: > * nobody is directly calling device_cold_reset() or > qdev_reset_all() on CPU objects > * no CPU object is on a qbus, so they will not be reset either > by somebody calling qbus_reset_all()/bus_cold_reset(), or > by the main "reset sysbus and everything in the qbus tree" > reset that most devices are reset by > > Note that this does not change the need for each machine or whatever > to use qemu_register_reset() to arrange to call cpu_reset() -- that > is necessary because CPU objects are not on any qbus, so they don't > get reset when the qbus tree rooted at the sysbus bus is reset, and > this isn't being changed here. > > All the changes to the files under target/ were made using the > included Coccinelle script, except: > > (1) the deletion of the now-inaccurate and not terribly useful > "CPUClass::reset" comments was done with a perl one-liner afterwards: > perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c > > (2) this bit of the s390 change was done by hand, because the > Coccinelle script is not sophisticated enough to handle the > parent_reset call being inside another function: > > | @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type) > | S390CPU *cpu = S390_CPU(s); > | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); > | CPUS390XState *env = &cpu->env; > |+ DeviceState *dev = DEVICE(s); > | > |- scc->parent_reset(s); > |+ scc->parent_reset(dev); > | cpu->env.sigp_order = 0; > | s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu); > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org> > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> > --- > hw/core/cpu.c | 19 +++--------- > include/hw/core/cpu.h | 6 ---- > scripts/coccinelle/cpu-reset.cocci | 47 ++++++++++++++++++++++++++++++ > target/alpha/cpu-qom.h | 2 +- > target/arm/cpu-qom.h | 2 +- > target/arm/cpu.c | 8 ++--- > target/cris/cpu-qom.h | 2 +- > target/cris/cpu.c | 8 ++--- > target/hppa/cpu-qom.h | 2 +- > target/i386/cpu-qom.h | 2 +- > target/i386/cpu.c | 8 ++--- > target/lm32/cpu-qom.h | 2 +- > target/lm32/cpu.c | 8 ++--- > target/m68k/cpu-qom.h | 2 +- > target/m68k/cpu.c | 8 ++--- > target/microblaze/cpu-qom.h | 2 +- > target/microblaze/cpu.c | 8 ++--- > target/mips/cpu-qom.h | 2 +- > target/mips/cpu.c | 8 ++--- > target/moxie/cpu.c | 7 +++-- > target/moxie/cpu.h | 2 +- > target/nios2/cpu.c | 8 ++--- > target/nios2/cpu.h | 2 +- > target/openrisc/cpu.c | 8 ++--- > target/openrisc/cpu.h | 2 +- > target/ppc/cpu-qom.h | 2 +- > target/ppc/translate_init.inc.c | 8 ++--- > target/riscv/cpu.c | 7 +++-- > target/riscv/cpu.h | 2 +- > target/s390x/cpu-qom.h | 2 +- > target/s390x/cpu.c | 8 +++-- > target/sh4/cpu-qom.h | 2 +- > target/sh4/cpu.c | 8 ++--- > target/sparc/cpu-qom.h | 2 +- > target/sparc/cpu.c | 8 ++--- > target/tilegx/cpu.c | 7 +++-- > target/tilegx/cpu.h | 2 +- > target/tricore/cpu-qom.h | 2 +- > target/tricore/cpu.c | 7 +++-- > target/xtensa/cpu-qom.h | 2 +- > target/xtensa/cpu.c | 8 ++--- > 41 files changed, 144 insertions(+), 108 deletions(-) > create mode 100644 scripts/coccinelle/cpu-reset.cocci > > diff --git a/hw/core/cpu.c b/hw/core/cpu.c > index fe65ca62ac..b889878f3c 100644 > --- a/hw/core/cpu.c > +++ b/hw/core/cpu.c > @@ -239,27 +239,16 @@ void cpu_dump_statistics(CPUState *cpu, int flags) > } > } > > -void cpu_class_set_parent_reset(CPUClass *cc, > - void (*child_reset)(CPUState *cpu), > - void (**parent_reset)(CPUState *cpu)) > -{ > - *parent_reset = cc->reset; > - cc->reset = child_reset; > -} > - > void cpu_reset(CPUState *cpu) > { > - CPUClass *klass = CPU_GET_CLASS(cpu); > - > - if (klass->reset != NULL) { > - (*klass->reset)(cpu); > - } > + device_cold_reset(DEVICE(cpu)); > > trace_guest_cpu_reset(cpu); > } > > -static void cpu_common_reset(CPUState *cpu) > +static void cpu_common_reset(DeviceState *dev) > { > + CPUState *cpu = CPU(dev); > CPUClass *cc = CPU_GET_CLASS(cpu); > > if (qemu_loglevel_mask(CPU_LOG_RESET)) { > @@ -419,7 +408,6 @@ static void cpu_class_init(ObjectClass *klass, void *data) > CPUClass *k = CPU_CLASS(klass); > > k->parse_features = cpu_common_parse_features; > - k->reset = cpu_common_reset; > k->get_arch_id = cpu_common_get_arch_id; > k->has_work = cpu_common_has_work; > k->get_paging_enabled = cpu_common_get_paging_enabled; > @@ -440,6 +428,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) > set_bit(DEVICE_CATEGORY_CPU, dc->categories); > dc->realize = cpu_common_realizefn; > dc->unrealize = cpu_common_unrealizefn; > + dc->reset = cpu_common_reset; > device_class_set_props(dc, cpu_common_props); > /* > * Reason: CPUs still need special care by board code: wiring up > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > index 73e9a869a4..88ee543722 100644 > --- a/include/hw/core/cpu.h > +++ b/include/hw/core/cpu.h > @@ -79,7 +79,6 @@ struct TranslationBlock; > * @class_by_name: Callback to map -cpu command line model name to an > * instantiatable CPU type. > * @parse_features: Callback to parse command line arguments. > - * @reset: Callback to reset the #CPUState to its initial state. > * @reset_dump_flags: #CPUDumpFlags to use for reset logging. > * @has_work: Callback for checking if there is work to do. > * @do_interrupt: Callback for interrupt handling. > @@ -165,7 +164,6 @@ typedef struct CPUClass { > ObjectClass *(*class_by_name)(const char *cpu_model); > void (*parse_features)(const char *typename, char *str, Error **errp); > > - void (*reset)(CPUState *cpu); Unfortunately this is going to clash with the "Add the Renesas RX architecture" series: https://www.mail-archive.com/qemu-devel@nongnu.org/msg689956.html Peter, due to the different set of testing and the timezone lag with Eduardo, I suggest you skip the RX pull request and I repost the pull request once this patch is merged. > int reset_dump_flags; > bool (*has_work)(CPUState *cpu); > void (*do_interrupt)(CPUState *cpu); > @@ -1135,10 +1133,6 @@ void cpu_exec_unrealizefn(CPUState *cpu); > */ > bool target_words_bigendian(void); > > -void cpu_class_set_parent_reset(CPUClass *cc, > - void (*child_reset)(CPUState *cpu), > - void (**parent_reset)(CPUState *cpu)); > - > #ifdef NEED_CPU_H > > #ifdef CONFIG_SOFTMMU > diff --git a/scripts/coccinelle/cpu-reset.cocci b/scripts/coccinelle/cpu-reset.cocci > new file mode 100644 > index 0000000000..396a724e51 > --- /dev/null > +++ b/scripts/coccinelle/cpu-reset.cocci > @@ -0,0 +1,47 @@ > +// Convert targets using the old CPUState reset to DeviceState reset > +// > +// Copyright Linaro Ltd 2020 > +// This work is licensed under the terms of the GNU GPLv2 or later. > +// > +// spatch --macro-file scripts/cocci-macro-file.h \ > +// --sp-file scripts/coccinelle/cpu-reset.cocci \ > +// --keep-comments --smpl-spacing --in-place --include-headers --dir target > +// > +// For simplicity we assume some things about the code we're modifying > +// that happen to be true for all our targets: > +// * all cpu_class_set_parent_reset() callsites have a 'DeviceClass *dc' local > +// * the parent reset field in the target CPU class is 'parent_reset' > +// * no reset function already has a 'dev' local > + > +@@ > +identifier cpu, x; > +typedef CPUState; > +@@ > +struct x { > +... > +- void (*parent_reset)(CPUState *cpu); > ++ DeviceReset parent_reset; > +... > +}; > +@ rule1 @ > +identifier resetfn; > +expression resetfield; > +identifier cc; > +@@ > +- cpu_class_set_parent_reset(cc, resetfn, resetfield) > ++ device_class_set_parent_reset(dc, resetfn, resetfield) > +@@ > +identifier rule1.resetfn; > +identifier cpu, cc; > +typedef CPUState, DeviceState; > +@@ > +-resetfn(CPUState *cpu) > +-{ > ++resetfn(DeviceState *dev) > ++{ > ++ CPUState *cpu = CPU(dev); > +<... > +- cc->parent_reset(cpu); > ++ cc->parent_reset(dev); > +...> > +} > diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h > index 6f0a0adb9e..08832fa767 100644 > --- a/target/alpha/cpu-qom.h > +++ b/target/alpha/cpu-qom.h > @@ -44,7 +44,7 @@ typedef struct AlphaCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } AlphaCPUClass; > > typedef struct AlphaCPU AlphaCPU; > diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h > index 3a9d31ea9d..d95568bf05 100644 > --- a/target/arm/cpu-qom.h > +++ b/target/arm/cpu-qom.h > @@ -51,7 +51,7 @@ typedef struct ARMCPUClass { > > const ARMCPUInfo *info; > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } ARMCPUClass; > > typedef struct ARMCPU ARMCPU; > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 7fe367078c..8e5ba619a0 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -155,14 +155,14 @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) > assert(oldvalue == newvalue); > } > > -/* CPUClass::reset() */ > -static void arm_cpu_reset(CPUState *s) > +static void arm_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > ARMCPU *cpu = ARM_CPU(s); > ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); > CPUARMState *env = &cpu->env; > > - acc->parent_reset(s); > + acc->parent_reset(dev); > > memset(env, 0, offsetof(CPUARMState, end_reset_fields)); > > @@ -2785,7 +2785,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) > &acc->parent_realize); > > device_class_set_props(dc, arm_cpu_properties); > - cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset); > + device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); > > cc->class_by_name = arm_cpu_class_by_name; > cc->has_work = arm_cpu_has_work; > diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h > index 308c1f95bd..f1de6041dc 100644 > --- a/target/cris/cpu-qom.h > +++ b/target/cris/cpu-qom.h > @@ -45,7 +45,7 @@ typedef struct CRISCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > > uint32_t vr; > } CRISCPUClass; > diff --git a/target/cris/cpu.c b/target/cris/cpu.c > index 17c6712e29..cff6b9eabf 100644 > --- a/target/cris/cpu.c > +++ b/target/cris/cpu.c > @@ -40,15 +40,15 @@ static bool cris_cpu_has_work(CPUState *cs) > return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); > } > > -/* CPUClass::reset() */ > -static void cris_cpu_reset(CPUState *s) > +static void cris_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > CRISCPU *cpu = CRIS_CPU(s); > CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); > CPUCRISState *env = &cpu->env; > uint32_t vr; > > - ccc->parent_reset(s); > + ccc->parent_reset(dev); > > vr = env->pregs[PR_VR]; > memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); > @@ -264,7 +264,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) > device_class_set_parent_realize(dc, cris_cpu_realizefn, > &ccc->parent_realize); > > - cpu_class_set_parent_reset(cc, cris_cpu_reset, &ccc->parent_reset); > + device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); > > cc->class_by_name = cris_cpu_class_by_name; > cc->has_work = cris_cpu_has_work; > diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h > index 6367dc4793..b1f6045495 100644 > --- a/target/hppa/cpu-qom.h > +++ b/target/hppa/cpu-qom.h > @@ -44,7 +44,7 @@ typedef struct HPPACPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } HPPACPUClass; > > typedef struct HPPACPU HPPACPU; > diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h > index 0efab2fc67..3e96f8d668 100644 > --- a/target/i386/cpu-qom.h > +++ b/target/i386/cpu-qom.h > @@ -71,7 +71,7 @@ typedef struct X86CPUClass { > > DeviceRealize parent_realize; > DeviceUnrealize parent_unrealize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } X86CPUClass; > > typedef struct X86CPU X86CPU; > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 350b51b346..fb3f3c54bb 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -5983,9 +5983,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > } > } > > -/* CPUClass::reset() */ > -static void x86_cpu_reset(CPUState *s) > +static void x86_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > X86CPU *cpu = X86_CPU(s); > X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); > CPUX86State *env = &cpu->env; > @@ -5993,7 +5993,7 @@ static void x86_cpu_reset(CPUState *s) > uint64_t xcr0; > int i; > > - xcc->parent_reset(s); > + xcc->parent_reset(dev); > > memset(env, 0, offsetof(CPUX86State, end_reset_fields)); > > @@ -7297,7 +7297,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) > &xcc->parent_unrealize); > device_class_set_props(dc, x86_cpu_properties); > > - cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset); > + device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset); > cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; > > cc->class_by_name = x86_cpu_class_by_name; > diff --git a/target/lm32/cpu-qom.h b/target/lm32/cpu-qom.h > index dc9ac9ac9f..bdedb3759a 100644 > --- a/target/lm32/cpu-qom.h > +++ b/target/lm32/cpu-qom.h > @@ -44,7 +44,7 @@ typedef struct LM32CPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } LM32CPUClass; > > typedef struct LM32CPU LM32CPU; > diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c > index 687bf35e65..c50ad5fa15 100644 > --- a/target/lm32/cpu.c > +++ b/target/lm32/cpu.c > @@ -99,14 +99,14 @@ static bool lm32_cpu_has_work(CPUState *cs) > return cs->interrupt_request & CPU_INTERRUPT_HARD; > } > > -/* CPUClass::reset() */ > -static void lm32_cpu_reset(CPUState *s) > +static void lm32_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > LM32CPU *cpu = LM32_CPU(s); > LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu); > CPULM32State *env = &cpu->env; > > - lcc->parent_reset(s); > + lcc->parent_reset(dev); > > /* reset cpu state */ > memset(env, 0, offsetof(CPULM32State, end_reset_fields)); > @@ -218,7 +218,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) > > device_class_set_parent_realize(dc, lm32_cpu_realizefn, > &lcc->parent_realize); > - cpu_class_set_parent_reset(cc, lm32_cpu_reset, &lcc->parent_reset); > + device_class_set_parent_reset(dc, lm32_cpu_reset, &lcc->parent_reset); > > cc->class_by_name = lm32_cpu_class_by_name; > cc->has_work = lm32_cpu_has_work; > diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h > index b56da8a213..88b11b60f1 100644 > --- a/target/m68k/cpu-qom.h > +++ b/target/m68k/cpu-qom.h > @@ -44,7 +44,7 @@ typedef struct M68kCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } M68kCPUClass; > > typedef struct M68kCPU M68kCPU; > diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c > index f0653cda2f..9445fcd6df 100644 > --- a/target/m68k/cpu.c > +++ b/target/m68k/cpu.c > @@ -41,16 +41,16 @@ static void m68k_set_feature(CPUM68KState *env, int feature) > env->features |= (1u << feature); > } > > -/* CPUClass::reset() */ > -static void m68k_cpu_reset(CPUState *s) > +static void m68k_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > M68kCPU *cpu = M68K_CPU(s); > M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu); > CPUM68KState *env = &cpu->env; > floatx80 nan = floatx80_default_nan(NULL); > int i; > > - mcc->parent_reset(s); > + mcc->parent_reset(dev); > > memset(env, 0, offsetof(CPUM68KState, end_reset_fields)); > #ifdef CONFIG_SOFTMMU > @@ -273,7 +273,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) > > device_class_set_parent_realize(dc, m68k_cpu_realizefn, > &mcc->parent_realize); > - cpu_class_set_parent_reset(cc, m68k_cpu_reset, &mcc->parent_reset); > + device_class_set_parent_reset(dc, m68k_cpu_reset, &mcc->parent_reset); > > cc->class_by_name = m68k_cpu_class_by_name; > cc->has_work = m68k_cpu_has_work; > diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h > index 49b07cc697..053ba44ee8 100644 > --- a/target/microblaze/cpu-qom.h > +++ b/target/microblaze/cpu-qom.h > @@ -44,7 +44,7 @@ typedef struct MicroBlazeCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } MicroBlazeCPUClass; > > typedef struct MicroBlazeCPU MicroBlazeCPU; > diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c > index 8c90110e52..a2c2f271df 100644 > --- a/target/microblaze/cpu.c > +++ b/target/microblaze/cpu.c > @@ -102,14 +102,14 @@ static void microblaze_cpu_set_irq(void *opaque, int irq, int level) > } > #endif > > -/* CPUClass::reset() */ > -static void mb_cpu_reset(CPUState *s) > +static void mb_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); > MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); > CPUMBState *env = &cpu->env; > > - mcc->parent_reset(s); > + mcc->parent_reset(dev); > > memset(env, 0, offsetof(CPUMBState, end_reset_fields)); > env->res_addr = RES_ADDR_NONE; > @@ -292,7 +292,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) > > device_class_set_parent_realize(dc, mb_cpu_realizefn, > &mcc->parent_realize); > - cpu_class_set_parent_reset(cc, mb_cpu_reset, &mcc->parent_reset); > + device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset); > > cc->class_by_name = mb_cpu_class_by_name; > cc->has_work = mb_cpu_has_work; > diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h > index a430c0fe4b..9d0df6c034 100644 > --- a/target/mips/cpu-qom.h > +++ b/target/mips/cpu-qom.h > @@ -48,7 +48,7 @@ typedef struct MIPSCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > const struct mips_def_t *cpu_def; > } MIPSCPUClass; > > diff --git a/target/mips/cpu.c b/target/mips/cpu.c > index 6cd6b9650b..e86cd06548 100644 > --- a/target/mips/cpu.c > +++ b/target/mips/cpu.c > @@ -96,14 +96,14 @@ static bool mips_cpu_has_work(CPUState *cs) > return has_work; > } > > -/* CPUClass::reset() */ > -static void mips_cpu_reset(CPUState *s) > +static void mips_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > MIPSCPU *cpu = MIPS_CPU(s); > MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); > CPUMIPSState *env = &cpu->env; > > - mcc->parent_reset(s); > + mcc->parent_reset(dev); > > memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); > > @@ -189,7 +189,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) > > device_class_set_parent_realize(dc, mips_cpu_realizefn, > &mcc->parent_realize); > - cpu_class_set_parent_reset(cc, mips_cpu_reset, &mcc->parent_reset); > + device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset); > > cc->class_by_name = mips_cpu_class_by_name; > cc->has_work = mips_cpu_has_work; > diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c > index cf47bc709b..6e0443ccb7 100644 > --- a/target/moxie/cpu.c > +++ b/target/moxie/cpu.c > @@ -35,13 +35,14 @@ static bool moxie_cpu_has_work(CPUState *cs) > return cs->interrupt_request & CPU_INTERRUPT_HARD; > } > > -static void moxie_cpu_reset(CPUState *s) > +static void moxie_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > MoxieCPU *cpu = MOXIE_CPU(s); > MoxieCPUClass *mcc = MOXIE_CPU_GET_CLASS(cpu); > CPUMoxieState *env = &cpu->env; > > - mcc->parent_reset(s); > + mcc->parent_reset(dev); > > memset(env, 0, offsetof(CPUMoxieState, end_reset_fields)); > env->pc = 0x1000; > @@ -101,7 +102,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data) > > device_class_set_parent_realize(dc, moxie_cpu_realizefn, > &mcc->parent_realize); > - cpu_class_set_parent_reset(cc, moxie_cpu_reset, &mcc->parent_reset); > + device_class_set_parent_reset(dc, moxie_cpu_reset, &mcc->parent_reset); > > cc->class_by_name = moxie_cpu_class_by_name; > > diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h > index 01dca548e5..455553b794 100644 > --- a/target/moxie/cpu.h > +++ b/target/moxie/cpu.h > @@ -69,7 +69,7 @@ typedef struct MoxieCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } MoxieCPUClass; > > /** > diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c > index 1c0c855a6f..0a4075949e 100644 > --- a/target/nios2/cpu.c > +++ b/target/nios2/cpu.c > @@ -39,9 +39,9 @@ static bool nios2_cpu_has_work(CPUState *cs) > return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); > } > > -/* CPUClass::reset() */ > -static void nios2_cpu_reset(CPUState *cs) > +static void nios2_cpu_reset(DeviceState *dev) > { > + CPUState *cs = CPU(dev); > Nios2CPU *cpu = NIOS2_CPU(cs); > Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu); > CPUNios2State *env = &cpu->env; > @@ -51,7 +51,7 @@ static void nios2_cpu_reset(CPUState *cs) > log_cpu_state(cs, 0); > } > > - ncc->parent_reset(cs); > + ncc->parent_reset(dev); > > memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS); > env->regs[R_PC] = cpu->reset_addr; > @@ -188,7 +188,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) > device_class_set_parent_realize(dc, nios2_cpu_realizefn, > &ncc->parent_realize); > device_class_set_props(dc, nios2_properties); > - cpu_class_set_parent_reset(cc, nios2_cpu_reset, &ncc->parent_reset); > + device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset); > > cc->class_by_name = nios2_cpu_class_by_name; > cc->has_work = nios2_cpu_has_work; > diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h > index 78f633f970..4dddf9c3a1 100644 > --- a/target/nios2/cpu.h > +++ b/target/nios2/cpu.h > @@ -50,7 +50,7 @@ typedef struct Nios2CPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } Nios2CPUClass; > > #define TARGET_HAS_ICE 1 > diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c > index 5cd04dafab..5528c0918f 100644 > --- a/target/openrisc/cpu.c > +++ b/target/openrisc/cpu.c > @@ -41,13 +41,13 @@ static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) > info->print_insn = print_insn_or1k; > } > > -/* CPUClass::reset() */ > -static void openrisc_cpu_reset(CPUState *s) > +static void openrisc_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > OpenRISCCPU *cpu = OPENRISC_CPU(s); > OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); > > - occ->parent_reset(s); > + occ->parent_reset(dev); > > memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); > > @@ -150,7 +150,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) > > device_class_set_parent_realize(dc, openrisc_cpu_realizefn, > &occ->parent_realize); > - cpu_class_set_parent_reset(cc, openrisc_cpu_reset, &occ->parent_reset); > + device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset); > > cc->class_by_name = openrisc_cpu_class_by_name; > cc->has_work = openrisc_cpu_has_work; > diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h > index 0ad02eab79..e7fb06445e 100644 > --- a/target/openrisc/cpu.h > +++ b/target/openrisc/cpu.h > @@ -48,7 +48,7 @@ typedef struct OpenRISCCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } OpenRISCCPUClass; > > #define TARGET_INSN_START_EXTRA_WORDS 1 > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h > index e499575dc8..b528131761 100644 > --- a/target/ppc/cpu-qom.h > +++ b/target/ppc/cpu-qom.h > @@ -166,7 +166,7 @@ typedef struct PowerPCCPUClass { > > DeviceRealize parent_realize; > DeviceUnrealize parent_unrealize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > void (*parent_parse_features)(const char *type, char *str, Error **errp); > > uint32_t pvr; > diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c > index 53995f62ea..7e9780e875 100644 > --- a/target/ppc/translate_init.inc.c > +++ b/target/ppc/translate_init.inc.c > @@ -10669,16 +10669,16 @@ static bool ppc_cpu_has_work(CPUState *cs) > return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); > } > > -/* CPUClass::reset() */ > -static void ppc_cpu_reset(CPUState *s) > +static void ppc_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > PowerPCCPU *cpu = POWERPC_CPU(s); > PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); > CPUPPCState *env = &cpu->env; > target_ulong msr; > int i; > > - pcc->parent_reset(s); > + pcc->parent_reset(dev); > > msr = (target_ulong)0; > msr |= (target_ulong)MSR_HVB; > @@ -10885,7 +10885,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) > pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; > device_class_set_props(dc, ppc_cpu_properties); > > - cpu_class_set_parent_reset(cc, ppc_cpu_reset, &pcc->parent_reset); > + device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); > > cc->class_by_name = ppc_cpu_class_by_name; > pcc->parent_parse_features = cc->parse_features; > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index c0b7023100..4e578239d3 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -330,13 +330,14 @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, > env->pc = data[0]; > } > > -static void riscv_cpu_reset(CPUState *cs) > +static void riscv_cpu_reset(DeviceState *dev) > { > + CPUState *cs = CPU(dev); > RISCVCPU *cpu = RISCV_CPU(cs); > RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); > CPURISCVState *env = &cpu->env; > > - mcc->parent_reset(cs); > + mcc->parent_reset(dev); > #ifndef CONFIG_USER_ONLY > env->priv = PRV_M; > env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); > @@ -511,7 +512,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) > device_class_set_parent_realize(dc, riscv_cpu_realize, > &mcc->parent_realize); > > - cpu_class_set_parent_reset(cc, riscv_cpu_reset, &mcc->parent_reset); > + device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); > > cc->class_by_name = riscv_cpu_class_by_name; > cc->has_work = riscv_cpu_has_work; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 3dcdf92227..078fc83959 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -234,7 +234,7 @@ typedef struct RISCVCPUClass { > CPUClass parent_class; > /*< public >*/ > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } RISCVCPUClass; > > /** > diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h > index dbe5346ec9..1630818c28 100644 > --- a/target/s390x/cpu-qom.h > +++ b/target/s390x/cpu-qom.h > @@ -61,7 +61,7 @@ typedef struct S390CPUClass { > const char *desc; > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > void (*load_normal)(CPUState *cpu); > void (*reset)(CPUState *cpu, cpu_reset_type type); > } S390CPUClass; > diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c > index 3dd396e870..427a46e3e1 100644 > --- a/target/s390x/cpu.c > +++ b/target/s390x/cpu.c > @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type) > S390CPU *cpu = S390_CPU(s); > S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); > CPUS390XState *env = &cpu->env; > + DeviceState *dev = DEVICE(s); > > - scc->parent_reset(s); > + scc->parent_reset(dev); > cpu->env.sigp_order = 0; > s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu); > > @@ -450,8 +451,9 @@ static Property s390x_cpu_properties[] = { > DEFINE_PROP_END_OF_LIST() > }; > > -static void s390_cpu_reset_full(CPUState *s) > +static void s390_cpu_reset_full(DeviceState *dev) > { > + CPUState *s = CPU(dev); > return s390_cpu_reset(s, S390_CPU_RESET_CLEAR); > } > > @@ -466,7 +468,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) > device_class_set_props(dc, s390x_cpu_properties); > dc->user_creatable = true; > > - cpu_class_set_parent_reset(cc, s390_cpu_reset_full, &scc->parent_reset); > + device_class_set_parent_reset(dc, s390_cpu_reset_full, &scc->parent_reset); > #if !defined(CONFIG_USER_ONLY) > scc->load_normal = s390_cpu_load_normal; > #endif > diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h > index 0c56d055ba..72a63f3fd3 100644 > --- a/target/sh4/cpu-qom.h > +++ b/target/sh4/cpu-qom.h > @@ -51,7 +51,7 @@ typedef struct SuperHCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > > uint32_t pvr; > uint32_t prr; > diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c > index 70c8d8170f..3c68021c56 100644 > --- a/target/sh4/cpu.c > +++ b/target/sh4/cpu.c > @@ -47,14 +47,14 @@ static bool superh_cpu_has_work(CPUState *cs) > return cs->interrupt_request & CPU_INTERRUPT_HARD; > } > > -/* CPUClass::reset() */ > -static void superh_cpu_reset(CPUState *s) > +static void superh_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > SuperHCPU *cpu = SUPERH_CPU(s); > SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); > CPUSH4State *env = &cpu->env; > > - scc->parent_reset(s); > + scc->parent_reset(dev); > > memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); > > @@ -214,7 +214,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) > device_class_set_parent_realize(dc, superh_cpu_realizefn, > &scc->parent_realize); > > - cpu_class_set_parent_reset(cc, superh_cpu_reset, &scc->parent_reset); > + device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset); > > cc->class_by_name = superh_cpu_class_by_name; > cc->has_work = superh_cpu_has_work; > diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h > index 7442e2768e..8b4d33c21e 100644 > --- a/target/sparc/cpu-qom.h > +++ b/target/sparc/cpu-qom.h > @@ -49,7 +49,7 @@ typedef struct SPARCCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > sparc_def_t *cpu_def; > } SPARCCPUClass; > > diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c > index eeaecbd8d6..3f05aba9d6 100644 > --- a/target/sparc/cpu.c > +++ b/target/sparc/cpu.c > @@ -28,14 +28,14 @@ > > //#define DEBUG_FEATURES > > -/* CPUClass::reset() */ > -static void sparc_cpu_reset(CPUState *s) > +static void sparc_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > SPARCCPU *cpu = SPARC_CPU(s); > SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu); > CPUSPARCState *env = &cpu->env; > > - scc->parent_reset(s); > + scc->parent_reset(dev); > > memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); > env->cwp = 0; > @@ -859,7 +859,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) > &scc->parent_realize); > device_class_set_props(dc, sparc_cpu_properties); > > - cpu_class_set_parent_reset(cc, sparc_cpu_reset, &scc->parent_reset); > + device_class_set_parent_reset(dc, sparc_cpu_reset, &scc->parent_reset); > > cc->class_by_name = sparc_cpu_class_by_name; > cc->parse_features = sparc_cpu_parse_features; > diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c > index cd422a0467..1fee87c094 100644 > --- a/target/tilegx/cpu.c > +++ b/target/tilegx/cpu.c > @@ -68,13 +68,14 @@ static bool tilegx_cpu_has_work(CPUState *cs) > return true; > } > > -static void tilegx_cpu_reset(CPUState *s) > +static void tilegx_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > TileGXCPU *cpu = TILEGX_CPU(s); > TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu); > CPUTLGState *env = &cpu->env; > > - tcc->parent_reset(s); > + tcc->parent_reset(dev); > > memset(env, 0, offsetof(CPUTLGState, end_reset_fields)); > } > @@ -142,7 +143,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data) > device_class_set_parent_realize(dc, tilegx_cpu_realizefn, > &tcc->parent_realize); > > - cpu_class_set_parent_reset(cc, tilegx_cpu_reset, &tcc->parent_reset); > + device_class_set_parent_reset(dc, tilegx_cpu_reset, &tcc->parent_reset); > > cc->class_by_name = tilegx_cpu_class_by_name; > cc->has_work = tilegx_cpu_has_work; > diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h > index 9cbec247d2..193b6bbccb 100644 > --- a/target/tilegx/cpu.h > +++ b/target/tilegx/cpu.h > @@ -118,7 +118,7 @@ typedef struct TileGXCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } TileGXCPUClass; > > /** > diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h > index 7c1e130b4e..cd819e6f24 100644 > --- a/target/tricore/cpu-qom.h > +++ b/target/tricore/cpu-qom.h > @@ -36,7 +36,7 @@ typedef struct TriCoreCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > } TriCoreCPUClass; > > typedef struct TriCoreCPU TriCoreCPU; > diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c > index 85bc9f03a1..743b404a95 100644 > --- a/target/tricore/cpu.c > +++ b/target/tricore/cpu.c > @@ -53,13 +53,14 @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs, > env->PC = tb->pc; > } > > -static void tricore_cpu_reset(CPUState *s) > +static void tricore_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > TriCoreCPU *cpu = TRICORE_CPU(s); > TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(cpu); > CPUTriCoreState *env = &cpu->env; > > - tcc->parent_reset(s); > + tcc->parent_reset(dev); > > cpu_state_reset(env); > } > @@ -153,7 +154,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) > device_class_set_parent_realize(dc, tricore_cpu_realizefn, > &mcc->parent_realize); > > - cpu_class_set_parent_reset(cc, tricore_cpu_reset, &mcc->parent_reset); > + device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_reset); > cc->class_by_name = tricore_cpu_class_by_name; > cc->has_work = tricore_cpu_has_work; > > diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h > index 9ac54241bd..3ea93ce1f9 100644 > --- a/target/xtensa/cpu-qom.h > +++ b/target/xtensa/cpu-qom.h > @@ -56,7 +56,7 @@ typedef struct XtensaCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - void (*parent_reset)(CPUState *cpu); > + DeviceReset parent_reset; > > const XtensaConfig *config; > } XtensaCPUClass; > diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c > index 4856aee8ec..82c2ee0679 100644 > --- a/target/xtensa/cpu.c > +++ b/target/xtensa/cpu.c > @@ -67,14 +67,14 @@ bool xtensa_abi_call0(void) > } > #endif > > -/* CPUClass::reset() */ > -static void xtensa_cpu_reset(CPUState *s) > +static void xtensa_cpu_reset(DeviceState *dev) > { > + CPUState *s = CPU(dev); > XtensaCPU *cpu = XTENSA_CPU(s); > XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); > CPUXtensaState *env = &cpu->env; > > - xcc->parent_reset(s); > + xcc->parent_reset(dev); > > env->exception_taken = 0; > env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; > @@ -184,7 +184,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) > device_class_set_parent_realize(dc, xtensa_cpu_realizefn, > &xcc->parent_realize); > > - cpu_class_set_parent_reset(cc, xtensa_cpu_reset, &xcc->parent_reset); > + device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset); > > cc->class_by_name = xtensa_cpu_class_by_name; > cc->has_work = xtensa_cpu_has_work; >
diff --git a/hw/core/cpu.c b/hw/core/cpu.c index fe65ca62ac..b889878f3c 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -239,27 +239,16 @@ void cpu_dump_statistics(CPUState *cpu, int flags) } } -void cpu_class_set_parent_reset(CPUClass *cc, - void (*child_reset)(CPUState *cpu), - void (**parent_reset)(CPUState *cpu)) -{ - *parent_reset = cc->reset; - cc->reset = child_reset; -} - void cpu_reset(CPUState *cpu) { - CPUClass *klass = CPU_GET_CLASS(cpu); - - if (klass->reset != NULL) { - (*klass->reset)(cpu); - } + device_cold_reset(DEVICE(cpu)); trace_guest_cpu_reset(cpu); } -static void cpu_common_reset(CPUState *cpu) +static void cpu_common_reset(DeviceState *dev) { + CPUState *cpu = CPU(dev); CPUClass *cc = CPU_GET_CLASS(cpu); if (qemu_loglevel_mask(CPU_LOG_RESET)) { @@ -419,7 +408,6 @@ static void cpu_class_init(ObjectClass *klass, void *data) CPUClass *k = CPU_CLASS(klass); k->parse_features = cpu_common_parse_features; - k->reset = cpu_common_reset; k->get_arch_id = cpu_common_get_arch_id; k->has_work = cpu_common_has_work; k->get_paging_enabled = cpu_common_get_paging_enabled; @@ -440,6 +428,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize = cpu_common_realizefn; dc->unrealize = cpu_common_unrealizefn; + dc->reset = cpu_common_reset; device_class_set_props(dc, cpu_common_props); /* * Reason: CPUs still need special care by board code: wiring up diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 73e9a869a4..88ee543722 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -79,7 +79,6 @@ struct TranslationBlock; * @class_by_name: Callback to map -cpu command line model name to an * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. - * @reset: Callback to reset the #CPUState to its initial state. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. * @do_interrupt: Callback for interrupt handling. @@ -165,7 +164,6 @@ typedef struct CPUClass { ObjectClass *(*class_by_name)(const char *cpu_model); void (*parse_features)(const char *typename, char *str, Error **errp); - void (*reset)(CPUState *cpu); int reset_dump_flags; bool (*has_work)(CPUState *cpu); void (*do_interrupt)(CPUState *cpu); @@ -1135,10 +1133,6 @@ void cpu_exec_unrealizefn(CPUState *cpu); */ bool target_words_bigendian(void); -void cpu_class_set_parent_reset(CPUClass *cc, - void (*child_reset)(CPUState *cpu), - void (**parent_reset)(CPUState *cpu)); - #ifdef NEED_CPU_H #ifdef CONFIG_SOFTMMU diff --git a/scripts/coccinelle/cpu-reset.cocci b/scripts/coccinelle/cpu-reset.cocci new file mode 100644 index 0000000000..396a724e51 --- /dev/null +++ b/scripts/coccinelle/cpu-reset.cocci @@ -0,0 +1,47 @@ +// Convert targets using the old CPUState reset to DeviceState reset +// +// Copyright Linaro Ltd 2020 +// This work is licensed under the terms of the GNU GPLv2 or later. +// +// spatch --macro-file scripts/cocci-macro-file.h \ +// --sp-file scripts/coccinelle/cpu-reset.cocci \ +// --keep-comments --smpl-spacing --in-place --include-headers --dir target +// +// For simplicity we assume some things about the code we're modifying +// that happen to be true for all our targets: +// * all cpu_class_set_parent_reset() callsites have a 'DeviceClass *dc' local +// * the parent reset field in the target CPU class is 'parent_reset' +// * no reset function already has a 'dev' local + +@@ +identifier cpu, x; +typedef CPUState; +@@ +struct x { +... +- void (*parent_reset)(CPUState *cpu); ++ DeviceReset parent_reset; +... +}; +@ rule1 @ +identifier resetfn; +expression resetfield; +identifier cc; +@@ +- cpu_class_set_parent_reset(cc, resetfn, resetfield) ++ device_class_set_parent_reset(dc, resetfn, resetfield) +@@ +identifier rule1.resetfn; +identifier cpu, cc; +typedef CPUState, DeviceState; +@@ +-resetfn(CPUState *cpu) +-{ ++resetfn(DeviceState *dev) ++{ ++ CPUState *cpu = CPU(dev); +<... +- cc->parent_reset(cpu); ++ cc->parent_reset(dev); +...> +} diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h index 6f0a0adb9e..08832fa767 100644 --- a/target/alpha/cpu-qom.h +++ b/target/alpha/cpu-qom.h @@ -44,7 +44,7 @@ typedef struct AlphaCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } AlphaCPUClass; typedef struct AlphaCPU AlphaCPU; diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 3a9d31ea9d..d95568bf05 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -51,7 +51,7 @@ typedef struct ARMCPUClass { const ARMCPUInfo *info; DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } ARMCPUClass; typedef struct ARMCPU ARMCPU; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7fe367078c..8e5ba619a0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -155,14 +155,14 @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) assert(oldvalue == newvalue); } -/* CPUClass::reset() */ -static void arm_cpu_reset(CPUState *s) +static void arm_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); ARMCPU *cpu = ARM_CPU(s); ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); CPUARMState *env = &cpu->env; - acc->parent_reset(s); + acc->parent_reset(dev); memset(env, 0, offsetof(CPUARMState, end_reset_fields)); @@ -2785,7 +2785,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) &acc->parent_realize); device_class_set_props(dc, arm_cpu_properties); - cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset); + device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); cc->class_by_name = arm_cpu_class_by_name; cc->has_work = arm_cpu_has_work; diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h index 308c1f95bd..f1de6041dc 100644 --- a/target/cris/cpu-qom.h +++ b/target/cris/cpu-qom.h @@ -45,7 +45,7 @@ typedef struct CRISCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; uint32_t vr; } CRISCPUClass; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 17c6712e29..cff6b9eabf 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -40,15 +40,15 @@ static bool cris_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } -/* CPUClass::reset() */ -static void cris_cpu_reset(CPUState *s) +static void cris_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); CRISCPU *cpu = CRIS_CPU(s); CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); CPUCRISState *env = &cpu->env; uint32_t vr; - ccc->parent_reset(s); + ccc->parent_reset(dev); vr = env->pregs[PR_VR]; memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); @@ -264,7 +264,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, cris_cpu_realizefn, &ccc->parent_realize); - cpu_class_set_parent_reset(cc, cris_cpu_reset, &ccc->parent_reset); + device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); cc->class_by_name = cris_cpu_class_by_name; cc->has_work = cris_cpu_has_work; diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index 6367dc4793..b1f6045495 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -44,7 +44,7 @@ typedef struct HPPACPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } HPPACPUClass; typedef struct HPPACPU HPPACPU; diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index 0efab2fc67..3e96f8d668 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -71,7 +71,7 @@ typedef struct X86CPUClass { DeviceRealize parent_realize; DeviceUnrealize parent_unrealize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } X86CPUClass; typedef struct X86CPU X86CPU; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 350b51b346..fb3f3c54bb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5983,9 +5983,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } } -/* CPUClass::reset() */ -static void x86_cpu_reset(CPUState *s) +static void x86_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); X86CPU *cpu = X86_CPU(s); X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); CPUX86State *env = &cpu->env; @@ -5993,7 +5993,7 @@ static void x86_cpu_reset(CPUState *s) uint64_t xcr0; int i; - xcc->parent_reset(s); + xcc->parent_reset(dev); memset(env, 0, offsetof(CPUX86State, end_reset_fields)); @@ -7297,7 +7297,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) &xcc->parent_unrealize); device_class_set_props(dc, x86_cpu_properties); - cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset); + device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset); cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; cc->class_by_name = x86_cpu_class_by_name; diff --git a/target/lm32/cpu-qom.h b/target/lm32/cpu-qom.h index dc9ac9ac9f..bdedb3759a 100644 --- a/target/lm32/cpu-qom.h +++ b/target/lm32/cpu-qom.h @@ -44,7 +44,7 @@ typedef struct LM32CPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } LM32CPUClass; typedef struct LM32CPU LM32CPU; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 687bf35e65..c50ad5fa15 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -99,14 +99,14 @@ static bool lm32_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } -/* CPUClass::reset() */ -static void lm32_cpu_reset(CPUState *s) +static void lm32_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); LM32CPU *cpu = LM32_CPU(s); LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu); CPULM32State *env = &cpu->env; - lcc->parent_reset(s); + lcc->parent_reset(dev); /* reset cpu state */ memset(env, 0, offsetof(CPULM32State, end_reset_fields)); @@ -218,7 +218,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, lm32_cpu_realizefn, &lcc->parent_realize); - cpu_class_set_parent_reset(cc, lm32_cpu_reset, &lcc->parent_reset); + device_class_set_parent_reset(dc, lm32_cpu_reset, &lcc->parent_reset); cc->class_by_name = lm32_cpu_class_by_name; cc->has_work = lm32_cpu_has_work; diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h index b56da8a213..88b11b60f1 100644 --- a/target/m68k/cpu-qom.h +++ b/target/m68k/cpu-qom.h @@ -44,7 +44,7 @@ typedef struct M68kCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } M68kCPUClass; typedef struct M68kCPU M68kCPU; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index f0653cda2f..9445fcd6df 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -41,16 +41,16 @@ static void m68k_set_feature(CPUM68KState *env, int feature) env->features |= (1u << feature); } -/* CPUClass::reset() */ -static void m68k_cpu_reset(CPUState *s) +static void m68k_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); M68kCPU *cpu = M68K_CPU(s); M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu); CPUM68KState *env = &cpu->env; floatx80 nan = floatx80_default_nan(NULL); int i; - mcc->parent_reset(s); + mcc->parent_reset(dev); memset(env, 0, offsetof(CPUM68KState, end_reset_fields)); #ifdef CONFIG_SOFTMMU @@ -273,7 +273,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, m68k_cpu_realizefn, &mcc->parent_realize); - cpu_class_set_parent_reset(cc, m68k_cpu_reset, &mcc->parent_reset); + device_class_set_parent_reset(dc, m68k_cpu_reset, &mcc->parent_reset); cc->class_by_name = m68k_cpu_class_by_name; cc->has_work = m68k_cpu_has_work; diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h index 49b07cc697..053ba44ee8 100644 --- a/target/microblaze/cpu-qom.h +++ b/target/microblaze/cpu-qom.h @@ -44,7 +44,7 @@ typedef struct MicroBlazeCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } MicroBlazeCPUClass; typedef struct MicroBlazeCPU MicroBlazeCPU; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 8c90110e52..a2c2f271df 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -102,14 +102,14 @@ static void microblaze_cpu_set_irq(void *opaque, int irq, int level) } #endif -/* CPUClass::reset() */ -static void mb_cpu_reset(CPUState *s) +static void mb_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); CPUMBState *env = &cpu->env; - mcc->parent_reset(s); + mcc->parent_reset(dev); memset(env, 0, offsetof(CPUMBState, end_reset_fields)); env->res_addr = RES_ADDR_NONE; @@ -292,7 +292,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, mb_cpu_realizefn, &mcc->parent_realize); - cpu_class_set_parent_reset(cc, mb_cpu_reset, &mcc->parent_reset); + device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset); cc->class_by_name = mb_cpu_class_by_name; cc->has_work = mb_cpu_has_work; diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index a430c0fe4b..9d0df6c034 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -48,7 +48,7 @@ typedef struct MIPSCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; const struct mips_def_t *cpu_def; } MIPSCPUClass; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 6cd6b9650b..e86cd06548 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -96,14 +96,14 @@ static bool mips_cpu_has_work(CPUState *cs) return has_work; } -/* CPUClass::reset() */ -static void mips_cpu_reset(CPUState *s) +static void mips_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); MIPSCPU *cpu = MIPS_CPU(s); MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); CPUMIPSState *env = &cpu->env; - mcc->parent_reset(s); + mcc->parent_reset(dev); memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); @@ -189,7 +189,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); - cpu_class_set_parent_reset(cc, mips_cpu_reset, &mcc->parent_reset); + device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset); cc->class_by_name = mips_cpu_class_by_name; cc->has_work = mips_cpu_has_work; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index cf47bc709b..6e0443ccb7 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -35,13 +35,14 @@ static bool moxie_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } -static void moxie_cpu_reset(CPUState *s) +static void moxie_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); MoxieCPU *cpu = MOXIE_CPU(s); MoxieCPUClass *mcc = MOXIE_CPU_GET_CLASS(cpu); CPUMoxieState *env = &cpu->env; - mcc->parent_reset(s); + mcc->parent_reset(dev); memset(env, 0, offsetof(CPUMoxieState, end_reset_fields)); env->pc = 0x1000; @@ -101,7 +102,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, moxie_cpu_realizefn, &mcc->parent_realize); - cpu_class_set_parent_reset(cc, moxie_cpu_reset, &mcc->parent_reset); + device_class_set_parent_reset(dc, moxie_cpu_reset, &mcc->parent_reset); cc->class_by_name = moxie_cpu_class_by_name; diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 01dca548e5..455553b794 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -69,7 +69,7 @@ typedef struct MoxieCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } MoxieCPUClass; /** diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 1c0c855a6f..0a4075949e 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -39,9 +39,9 @@ static bool nios2_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } -/* CPUClass::reset() */ -static void nios2_cpu_reset(CPUState *cs) +static void nios2_cpu_reset(DeviceState *dev) { + CPUState *cs = CPU(dev); Nios2CPU *cpu = NIOS2_CPU(cs); Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu); CPUNios2State *env = &cpu->env; @@ -51,7 +51,7 @@ static void nios2_cpu_reset(CPUState *cs) log_cpu_state(cs, 0); } - ncc->parent_reset(cs); + ncc->parent_reset(dev); memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS); env->regs[R_PC] = cpu->reset_addr; @@ -188,7 +188,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, nios2_cpu_realizefn, &ncc->parent_realize); device_class_set_props(dc, nios2_properties); - cpu_class_set_parent_reset(cc, nios2_cpu_reset, &ncc->parent_reset); + device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset); cc->class_by_name = nios2_cpu_class_by_name; cc->has_work = nios2_cpu_has_work; diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 78f633f970..4dddf9c3a1 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -50,7 +50,7 @@ typedef struct Nios2CPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } Nios2CPUClass; #define TARGET_HAS_ICE 1 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 5cd04dafab..5528c0918f 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -41,13 +41,13 @@ static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) info->print_insn = print_insn_or1k; } -/* CPUClass::reset() */ -static void openrisc_cpu_reset(CPUState *s) +static void openrisc_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); OpenRISCCPU *cpu = OPENRISC_CPU(s); OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); - occ->parent_reset(s); + occ->parent_reset(dev); memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); @@ -150,7 +150,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, openrisc_cpu_realizefn, &occ->parent_realize); - cpu_class_set_parent_reset(cc, openrisc_cpu_reset, &occ->parent_reset); + device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset); cc->class_by_name = openrisc_cpu_class_by_name; cc->has_work = openrisc_cpu_has_work; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 0ad02eab79..e7fb06445e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -48,7 +48,7 @@ typedef struct OpenRISCCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } OpenRISCCPUClass; #define TARGET_INSN_START_EXTRA_WORDS 1 diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index e499575dc8..b528131761 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -166,7 +166,7 @@ typedef struct PowerPCCPUClass { DeviceRealize parent_realize; DeviceUnrealize parent_unrealize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; void (*parent_parse_features)(const char *type, char *str, Error **errp); uint32_t pvr; diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 53995f62ea..7e9780e875 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10669,16 +10669,16 @@ static bool ppc_cpu_has_work(CPUState *cs) return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); } -/* CPUClass::reset() */ -static void ppc_cpu_reset(CPUState *s) +static void ppc_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); PowerPCCPU *cpu = POWERPC_CPU(s); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env = &cpu->env; target_ulong msr; int i; - pcc->parent_reset(s); + pcc->parent_reset(dev); msr = (target_ulong)0; msr |= (target_ulong)MSR_HVB; @@ -10885,7 +10885,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; device_class_set_props(dc, ppc_cpu_properties); - cpu_class_set_parent_reset(cc, ppc_cpu_reset, &pcc->parent_reset); + device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); cc->class_by_name = ppc_cpu_class_by_name; pcc->parent_parse_features = cc->parse_features; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c0b7023100..4e578239d3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -330,13 +330,14 @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, env->pc = data[0]; } -static void riscv_cpu_reset(CPUState *cs) +static void riscv_cpu_reset(DeviceState *dev) { + CPUState *cs = CPU(dev); RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); CPURISCVState *env = &cpu->env; - mcc->parent_reset(cs); + mcc->parent_reset(dev); #ifndef CONFIG_USER_ONLY env->priv = PRV_M; env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); @@ -511,7 +512,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, riscv_cpu_realize, &mcc->parent_realize); - cpu_class_set_parent_reset(cc, riscv_cpu_reset, &mcc->parent_reset); + device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); cc->class_by_name = riscv_cpu_class_by_name; cc->has_work = riscv_cpu_has_work; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3dcdf92227..078fc83959 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -234,7 +234,7 @@ typedef struct RISCVCPUClass { CPUClass parent_class; /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } RISCVCPUClass; /** diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index dbe5346ec9..1630818c28 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -61,7 +61,7 @@ typedef struct S390CPUClass { const char *desc; DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; void (*load_normal)(CPUState *cpu); void (*reset)(CPUState *cpu, cpu_reset_type type); } S390CPUClass; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 3dd396e870..427a46e3e1 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type) S390CPU *cpu = S390_CPU(s); S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); CPUS390XState *env = &cpu->env; + DeviceState *dev = DEVICE(s); - scc->parent_reset(s); + scc->parent_reset(dev); cpu->env.sigp_order = 0; s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu); @@ -450,8 +451,9 @@ static Property s390x_cpu_properties[] = { DEFINE_PROP_END_OF_LIST() }; -static void s390_cpu_reset_full(CPUState *s) +static void s390_cpu_reset_full(DeviceState *dev) { + CPUState *s = CPU(dev); return s390_cpu_reset(s, S390_CPU_RESET_CLEAR); } @@ -466,7 +468,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) device_class_set_props(dc, s390x_cpu_properties); dc->user_creatable = true; - cpu_class_set_parent_reset(cc, s390_cpu_reset_full, &scc->parent_reset); + device_class_set_parent_reset(dc, s390_cpu_reset_full, &scc->parent_reset); #if !defined(CONFIG_USER_ONLY) scc->load_normal = s390_cpu_load_normal; #endif diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h index 0c56d055ba..72a63f3fd3 100644 --- a/target/sh4/cpu-qom.h +++ b/target/sh4/cpu-qom.h @@ -51,7 +51,7 @@ typedef struct SuperHCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; uint32_t pvr; uint32_t prr; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 70c8d8170f..3c68021c56 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -47,14 +47,14 @@ static bool superh_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } -/* CPUClass::reset() */ -static void superh_cpu_reset(CPUState *s) +static void superh_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); SuperHCPU *cpu = SUPERH_CPU(s); SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); CPUSH4State *env = &cpu->env; - scc->parent_reset(s); + scc->parent_reset(dev); memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); @@ -214,7 +214,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, superh_cpu_realizefn, &scc->parent_realize); - cpu_class_set_parent_reset(cc, superh_cpu_reset, &scc->parent_reset); + device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset); cc->class_by_name = superh_cpu_class_by_name; cc->has_work = superh_cpu_has_work; diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index 7442e2768e..8b4d33c21e 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -49,7 +49,7 @@ typedef struct SPARCCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; sparc_def_t *cpu_def; } SPARCCPUClass; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index eeaecbd8d6..3f05aba9d6 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -28,14 +28,14 @@ //#define DEBUG_FEATURES -/* CPUClass::reset() */ -static void sparc_cpu_reset(CPUState *s) +static void sparc_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); SPARCCPU *cpu = SPARC_CPU(s); SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu); CPUSPARCState *env = &cpu->env; - scc->parent_reset(s); + scc->parent_reset(dev); memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); env->cwp = 0; @@ -859,7 +859,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) &scc->parent_realize); device_class_set_props(dc, sparc_cpu_properties); - cpu_class_set_parent_reset(cc, sparc_cpu_reset, &scc->parent_reset); + device_class_set_parent_reset(dc, sparc_cpu_reset, &scc->parent_reset); cc->class_by_name = sparc_cpu_class_by_name; cc->parse_features = sparc_cpu_parse_features; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index cd422a0467..1fee87c094 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -68,13 +68,14 @@ static bool tilegx_cpu_has_work(CPUState *cs) return true; } -static void tilegx_cpu_reset(CPUState *s) +static void tilegx_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); TileGXCPU *cpu = TILEGX_CPU(s); TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu); CPUTLGState *env = &cpu->env; - tcc->parent_reset(s); + tcc->parent_reset(dev); memset(env, 0, offsetof(CPUTLGState, end_reset_fields)); } @@ -142,7 +143,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, tilegx_cpu_realizefn, &tcc->parent_realize); - cpu_class_set_parent_reset(cc, tilegx_cpu_reset, &tcc->parent_reset); + device_class_set_parent_reset(dc, tilegx_cpu_reset, &tcc->parent_reset); cc->class_by_name = tilegx_cpu_class_by_name; cc->has_work = tilegx_cpu_has_work; diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 9cbec247d2..193b6bbccb 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -118,7 +118,7 @@ typedef struct TileGXCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } TileGXCPUClass; /** diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h index 7c1e130b4e..cd819e6f24 100644 --- a/target/tricore/cpu-qom.h +++ b/target/tricore/cpu-qom.h @@ -36,7 +36,7 @@ typedef struct TriCoreCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } TriCoreCPUClass; typedef struct TriCoreCPU TriCoreCPU; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 85bc9f03a1..743b404a95 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -53,13 +53,14 @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs, env->PC = tb->pc; } -static void tricore_cpu_reset(CPUState *s) +static void tricore_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); TriCoreCPU *cpu = TRICORE_CPU(s); TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(cpu); CPUTriCoreState *env = &cpu->env; - tcc->parent_reset(s); + tcc->parent_reset(dev); cpu_state_reset(env); } @@ -153,7 +154,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, tricore_cpu_realizefn, &mcc->parent_realize); - cpu_class_set_parent_reset(cc, tricore_cpu_reset, &mcc->parent_reset); + device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_reset); cc->class_by_name = tricore_cpu_class_by_name; cc->has_work = tricore_cpu_has_work; diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h index 9ac54241bd..3ea93ce1f9 100644 --- a/target/xtensa/cpu-qom.h +++ b/target/xtensa/cpu-qom.h @@ -56,7 +56,7 @@ typedef struct XtensaCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; const XtensaConfig *config; } XtensaCPUClass; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 4856aee8ec..82c2ee0679 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -67,14 +67,14 @@ bool xtensa_abi_call0(void) } #endif -/* CPUClass::reset() */ -static void xtensa_cpu_reset(CPUState *s) +static void xtensa_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); XtensaCPU *cpu = XTENSA_CPU(s); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); CPUXtensaState *env = &cpu->env; - xcc->parent_reset(s); + xcc->parent_reset(dev); env->exception_taken = 0; env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; @@ -184,7 +184,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, xtensa_cpu_realizefn, &xcc->parent_realize); - cpu_class_set_parent_reset(cc, xtensa_cpu_reset, &xcc->parent_reset); + device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset); cc->class_by_name = xtensa_cpu_class_by_name; cc->has_work = xtensa_cpu_has_work;