diff mbox

[1/3] clk: exynos5250: Add G2D gate clock

Message ID 1373013749-14530-1-git-send-email-sachin.kamat@linaro.org
State Accepted
Headers show

Commit Message

Sachin Kamat July 5, 2013, 8:42 a.m. UTC
Adds gate clock for G2D IP for Exynos5250 SoC.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Mike Turquette <mturquette@linaro.org>
---
This patch depends on the following patch:
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581
---
 .../devicetree/bindings/clock/exynos5250-clock.txt |    1 +
 drivers/clk/samsung/clk-exynos5250.c               |    5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

Comments

Sachin Kamat July 26, 2013, 8:48 a.m. UTC | #1
On 5 July 2013 14:12, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> Adds gate clock for G2D IP for Exynos5250 SoC.
>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> Cc: Mike Turquette <mturquette@linaro.org>
> ---
> This patch depends on the following patch:
> http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581
> ---
>  .../devicetree/bindings/clock/exynos5250-clock.txt |    1 +
>  drivers/clk/samsung/clk-exynos5250.c               |    5 ++++-
>  2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> index 1a05761..7e88242 100644
> --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> @@ -155,6 +155,7 @@ clock which they consume.
>    dp                   342
>    mixer                        343
>    hdmi                 344
> +  g2d                  345
>
>  Example 1: An example of a clock controller node is listed below.
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index 6f767c5..3da0bdf 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -62,6 +62,7 @@
>  #define SRC_CDREX              0x20200
>  #define PLL_DIV2_SEL           0x20a24
>  #define GATE_IP_DISP1          0x10928
> +#define GATE_IP_ACP            0x10000
>
>  /*
>   * Let each supported clock get a unique id. This id is used to lookup the clock
> @@ -99,7 +100,7 @@ enum exynos5250_clks {
>         spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
>         hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
>         tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
> -       wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
> +       wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
>
>         nr_clks,
>  };
> @@ -152,6 +153,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
>         SRC_CDREX,
>         PLL_DIV2_SEL,
>         GATE_IP_DISP1,
> +       GATE_IP_ACP,
>  };
>
>  /* list of all parent clock list */
> @@ -463,6 +465,7 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
>         GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
>         GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
>         GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
> +       GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
>  };
>
>  static __initdata struct of_device_id ext_clk_match[] = {
> --
> 1.7.9.5
>

Ping Mike.
Mike Turquette July 26, 2013, 8:18 p.m. UTC | #2
Quoting Sachin Kamat (2013-07-05 01:42:27)
> Adds gate clock for G2D IP for Exynos5250 SoC.
> 
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> Cc: Mike Turquette <mturquette@linaro.org>

I've taken patch #1 into clk-next.

> ---
> This patch depends on the following patch:
> http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581

I think I've gotten all three series you sent out, can you confirm?
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/20829
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/20582

Regards,
Mike

> ---
>  .../devicetree/bindings/clock/exynos5250-clock.txt |    1 +
>  drivers/clk/samsung/clk-exynos5250.c               |    5 ++++-
>  2 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> index 1a05761..7e88242 100644
> --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> @@ -155,6 +155,7 @@ clock which they consume.
>    dp                   342
>    mixer                        343
>    hdmi                 344
> +  g2d                  345
>  
>  Example 1: An example of a clock controller node is listed below.
>  
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index 6f767c5..3da0bdf 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -62,6 +62,7 @@
>  #define SRC_CDREX              0x20200
>  #define PLL_DIV2_SEL           0x20a24
>  #define GATE_IP_DISP1          0x10928
> +#define GATE_IP_ACP            0x10000
>  
>  /*
>   * Let each supported clock get a unique id. This id is used to lookup the clock
> @@ -99,7 +100,7 @@ enum exynos5250_clks {
>         spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
>         hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
>         tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
> -       wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
> +       wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
>  
>         nr_clks,
>  };
> @@ -152,6 +153,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
>         SRC_CDREX,
>         PLL_DIV2_SEL,
>         GATE_IP_DISP1,
> +       GATE_IP_ACP,
>  };
>  
>  /* list of all parent clock list */
> @@ -463,6 +465,7 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
>         GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
>         GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
>         GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
> +       GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
>  };
>  
>  static __initdata struct of_device_id ext_clk_match[] = {
> -- 
> 1.7.9.5
Sachin Kamat July 27, 2013, 1:29 p.m. UTC | #3
On 27 July 2013 01:48, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Sachin Kamat (2013-07-05 01:42:27)
>> Adds gate clock for G2D IP for Exynos5250 SoC.
>>
>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>> Cc: Mike Turquette <mturquette@linaro.org>
>
> I've taken patch #1 into clk-next.

Thanks Mike.

>
>> ---
>> This patch depends on the following patch:
>> http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581
>
> I think I've gotten all three series you sent out, can you confirm?

I haven't seen any update in your tree [1] since quite some time. The
last commit I see in clk-next branch is 45e3ec3784 ("clk: tegra: fix
ifdef for tegra_periph_reset_assert inline"). I hope I am looking at
the right tree?

[1] git://git.linaro.org/people/mturquette/linux.git
Mike Turquette July 30, 2013, 6:48 a.m. UTC | #4
Quoting Sachin Kamat (2013-07-27 06:29:56)
> On 27 July 2013 01:48, Mike Turquette <mturquette@linaro.org> wrote:
> > Quoting Sachin Kamat (2013-07-05 01:42:27)
> >> Adds gate clock for G2D IP for Exynos5250 SoC.
> >>
> >> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> >> Cc: Mike Turquette <mturquette@linaro.org>
> >
> > I've taken patch #1 into clk-next.
> 
> Thanks Mike.
> 
> >
> >> ---
> >> This patch depends on the following patch:
> >> http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581
> >
> > I think I've gotten all three series you sent out, can you confirm?
> 
> I haven't seen any update in your tree [1] since quite some time. The
> last commit I see in clk-next branch is 45e3ec3784 ("clk: tegra: fix
> ifdef for tegra_periph_reset_assert inline"). I hope I am looking at
> the right tree?

You are, but I had not pushed to it since the merge window closed. It is
now updated.

Regards,
Mike

> 
> [1] git://git.linaro.org/people/mturquette/linux.git
> 
> -- 
> With warm regards,
> Sachin
Sachin Kamat July 30, 2013, 6:55 a.m. UTC | #5
On 30 July 2013 12:18, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Sachin Kamat (2013-07-27 06:29:56)
>> On 27 July 2013 01:48, Mike Turquette <mturquette@linaro.org> wrote:
>> > Quoting Sachin Kamat (2013-07-05 01:42:27)
>> >> Adds gate clock for G2D IP for Exynos5250 SoC.
>> >>
>> >> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>> >> Cc: Mike Turquette <mturquette@linaro.org>
>> >
>> > I've taken patch #1 into clk-next.
>>
>> Thanks Mike.
>>
>> >
>> >> ---
>> >> This patch depends on the following patch:
>> >> http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581
>> >
>> > I think I've gotten all three series you sent out, can you confirm?
>>
>> I haven't seen any update in your tree [1] since quite some time. The
>> last commit I see in clk-next branch is 45e3ec3784 ("clk: tegra: fix
>> ifdef for tegra_periph_reset_assert inline"). I hope I am looking at
>> the right tree?
>
> You are, but I had not pushed to it since the merge window closed. It is
> now updated.
>

Thanks Mike. I confirm that all the three patch series that you
mentioned are applied in your tree.
Please check the below one too.

http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg20598.html
Mike Turquette July 31, 2013, 3:42 a.m. UTC | #6
Quoting Sachin Kamat (2013-07-29 23:55:33)
> On 30 July 2013 12:18, Mike Turquette <mturquette@linaro.org> wrote:
> > Quoting Sachin Kamat (2013-07-27 06:29:56)
> >> On 27 July 2013 01:48, Mike Turquette <mturquette@linaro.org> wrote:
> >> > Quoting Sachin Kamat (2013-07-05 01:42:27)
> >> >> Adds gate clock for G2D IP for Exynos5250 SoC.
> >> >>
> >> >> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> >> >> Cc: Mike Turquette <mturquette@linaro.org>
> >> >
> >> > I've taken patch #1 into clk-next.
> >>
> >> Thanks Mike.
> >>
> >> >
> >> >> ---
> >> >> This patch depends on the following patch:
> >> >> http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581
> >> >
> >> > I think I've gotten all three series you sent out, can you confirm?
> >>
> >> I haven't seen any update in your tree [1] since quite some time. The
> >> last commit I see in clk-next branch is 45e3ec3784 ("clk: tegra: fix
> >> ifdef for tegra_periph_reset_assert inline"). I hope I am looking at
> >> the right tree?
> >
> > You are, but I had not pushed to it since the merge window closed. It is
> > now updated.
> >
> 
> Thanks Mike. I confirm that all the three patch series that you
> mentioned are applied in your tree.
> Please check the below one too.
> 
> http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg20598.html

Ok, I picked that one up too.

Regards,
Mike

> 
> -- 
> With warm regards,
> Sachin
Sachin Kamat July 31, 2013, 3:48 a.m. UTC | #7
On 31 July 2013 09:12, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Sachin Kamat (2013-07-29 23:55:33)
>> On 30 July 2013 12:18, Mike Turquette <mturquette@linaro.org> wrote:
>> > Quoting Sachin Kamat (2013-07-27 06:29:56)
>> >> On 27 July 2013 01:48, Mike Turquette <mturquette@linaro.org> wrote:
>> >> > Quoting Sachin Kamat (2013-07-05 01:42:27)
>> >> >> Adds gate clock for G2D IP for Exynos5250 SoC.
>> >> >>
>> >> >> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
>> >> >> Cc: Mike Turquette <mturquette@linaro.org>
>> >> >
>> >> > I've taken patch #1 into clk-next.
>> >>
>> >> Thanks Mike.
>> >>
>> >> >
>> >> >> ---
>> >> >> This patch depends on the following patch:
>> >> >> http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581
>> >> >
>> >> > I think I've gotten all three series you sent out, can you confirm?
>> >>
>> >> I haven't seen any update in your tree [1] since quite some time. The
>> >> last commit I see in clk-next branch is 45e3ec3784 ("clk: tegra: fix
>> >> ifdef for tegra_periph_reset_assert inline"). I hope I am looking at
>> >> the right tree?
>> >
>> > You are, but I had not pushed to it since the merge window closed. It is
>> > now updated.
>> >
>>
>> Thanks Mike. I confirm that all the three patch series that you
>> mentioned are applied in your tree.
>> Please check the below one too.
>>
>> http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg20598.html
>
> Ok, I picked that one up too.

Thanks Mike.
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 1a05761..7e88242 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -155,6 +155,7 @@  clock which they consume.
   dp			342
   mixer			343
   hdmi			344
+  g2d			345
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 6f767c5..3da0bdf 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -62,6 +62,7 @@ 
 #define SRC_CDREX		0x20200
 #define PLL_DIV2_SEL		0x20a24
 #define GATE_IP_DISP1		0x10928
+#define GATE_IP_ACP		0x10000
 
 /*
  * Let each supported clock get a unique id. This id is used to lookup the clock
@@ -99,7 +100,7 @@  enum exynos5250_clks {
 	spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
 	hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
 	tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
-	wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
+	wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
 
 	nr_clks,
 };
@@ -152,6 +153,7 @@  static __initdata unsigned long exynos5250_clk_regs[] = {
 	SRC_CDREX,
 	PLL_DIV2_SEL,
 	GATE_IP_DISP1,
+	GATE_IP_ACP,
 };
 
 /* list of all parent clock list */
@@ -463,6 +465,7 @@  struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
 	GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
 	GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
 	GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
+	GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
 };
 
 static __initdata struct of_device_id ext_clk_match[] = {