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[1/7] arm: exynos5250: Define CONFIG_SYS_CACHELINE_SIZE

Message ID 1372769977-7182-2-git-send-email-gautam.vivek@samsung.com
State Superseded
Headers show

Commit Message

Vivek Gautam July 2, 2013, 12:59 p.m. UTC 
XHCI stack driver needs this to align buffers to
CacheLine boundary. So define the same to be '64'

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
---
 include/configs/exynos5250-dt.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)
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Patch

diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index e2a096b..de76836 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -54,6 +54,8 @@ 
 /* Keep L2 Cache Disabled */
 #define CONFIG_SYS_DCACHE_OFF
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /* Enable ACE acceleration for SHA1 and SHA256 */
 #define CONFIG_EXYNOS_ACE_SHA
 #define CONFIG_SHA_HW_ACCEL