| Message ID | 20191203225333.17055-5-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Implement ARMv8.1-PAN + ARMv8.2-ATS1E1 | expand |
On Tue, 3 Dec 2019 at 22:53, Richard Henderson <richard.henderson@linaro.org> wrote: > > Since v8.0, the CPSR_RESERVED bits have been allocated. > We are not yet implementing ARMv8.4-DIT; retain CPSR_RESERVED, > since that overlaps with our current hack for AA32 single step. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 22c5706835..49dc436e5e 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1149,12 +1149,16 @@ void pmu_init(ARMCPU *cpu); > #define CPSR_IT_2_7 (0xfc00U) > #define CPSR_GE (0xfU << 16) > #define CPSR_IL (1U << 20) > -/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in > +/* > + * Note that the RESERVED bits include bit 21, which is PSTATE_SS in > * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use > * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, > * where it is live state but not accessible to the AArch32 code. > + * > + * TODO: With ARMv8.4-DIT, bit 21 is DIT in AArch32 (bit 24 for AArch64). > + * We will need to move AArch32 SS somewhere else at that point. > */ > -#define CPSR_RESERVED (0x7U << 21) > +#define CPSR_RESERVED (1U << 21) > #define CPSR_J (1U << 24) > #define CPSR_IT_0_1 (3U << 25) > #define CPSR_Q (1U << 27) Should we retain the current behaviour of forbidding guest writes to the CPSR (directly, or via exception return and SPSR->CPSR writes) from messing with the PAN and SSBS bits on CPUs which don't implement those features ? thanks -- PMM
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 22c5706835..49dc436e5e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1149,12 +1149,16 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) -/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in +/* + * Note that the RESERVED bits include bit 21, which is PSTATE_SS in * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, * where it is live state but not accessible to the AArch32 code. + * + * TODO: With ARMv8.4-DIT, bit 21 is DIT in AArch32 (bit 24 for AArch64). + * We will need to move AArch32 SS somewhere else at that point. */ -#define CPSR_RESERVED (0x7U << 21) +#define CPSR_RESERVED (1U << 21) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27)
Since v8.0, the CPSR_RESERVED bits have been allocated. We are not yet implementing ARMv8.4-DIT; retain CPSR_RESERVED, since that overlaps with our current hack for AA32 single step. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.17.1