[v4,2/8] irqchip: Add Realtek RTD1295 mux driver

Message ID	20191119021917.15917-3-afaerber@suse.de
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; From: =?utf-8?q?Andreas_F=C3=A4rber?= <afaerber@suse.de> To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= <afaerber@suse.de>, Aleix Roca Nonell <kernelrocks@gmail.com>, James Tai <james.tai@realtek.com>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <maz@kernel.org> Subject: [PATCH v4 2/8] irqchip: Add Realtek RTD1295 mux driver Date: Tue, 19 Nov 2019 03:19:11 +0100 Message-Id: <20191119021917.15917-3-afaerber@suse.de> In-Reply-To: <20191119021917.15917-1-afaerber@suse.de> References: <20191119021917.15917-1-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk
Series	ARM: Realtek RTD1195/RTD1295/RTD1395 IRQ mux \| expand [v4,0/8] ARM: Realtek RTD1195/RTD1295/RTD1395 IRQ mux [v4,2/8] irqchip: Add Realtek RTD1295 mux driver [v4,3/8] arm64: dts: realtek: rtd129x: Add irq muxes and UART interrupts [v4,4/8] irqchip: rtd1195-mux: Add RTD1195 definitions [v4,5/8] ARM: dts: rtd1195: Add irq muxes and UART interrupts [v4,6/8] dt-bindings: interrupt-controller: rtd1195-mux: Add RTD1395 [v4,7/8] irqchip: rtd1195-mux: Add RTD1395 definitions

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e806dda690ea..d678881eebc8 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -104,3 +104,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o +obj-$(CONFIG_ARCH_REALTEK) += irq-rtd1195-mux.o diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c new file mode 100644 index 000000000000..e6b08438b23c --- /dev/null +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek RTD1295 IRQ mux + * + * Copyright (c) 2017-2019 Andreas Färber + */ + +#include <linux/io.h> +#include <linux/irqchip.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/irqdomain.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/slab.h> + +struct rtd1195_irq_mux_info { + unsigned int isr_offset; + unsigned int umsk_isr_offset; + unsigned int scpu_int_en_offset; + const u32 *isr_to_int_en_mask; +}; + +struct rtd1195_irq_mux_data { + void __iomem *reg_isr; + void __iomem *reg_umsk_isr; + void __iomem *reg_scpu_int_en; + const struct rtd1195_irq_mux_info *info; + int irq; + u32 scpu_int_en; + struct irq_domain *domain; + raw_spinlock_t lock; +}; + +static void rtd1195_mux_irq_handle(struct irq_desc *desc) +{ + struct rtd1195_irq_mux_data *data = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 isr, mask; + int i; + + chained_irq_enter(chip, desc); + + isr = readl_relaxed(data->reg_isr); + + while (isr) { + i = __ffs(isr); + isr &= ~BIT(i); + + mask = data->info->isr_to_int_en_mask[i]; + if (mask && !(data->scpu_int_en & mask)) + continue; + + if (!generic_handle_irq(irq_find_mapping(data->domain, i))) + writel_relaxed(BIT(i), data->reg_isr); + } + + chained_irq_exit(chip, desc); +} + +static void rtd1195_mux_mask_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux_data = irq_data_get_irq_chip_data(data); + + writel_relaxed(BIT(data->hwirq), mux_data->reg_isr); +} + +static void rtd1195_mux_unmask_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux_data = irq_data_get_irq_chip_data(data); + + writel_relaxed(BIT(data->hwirq), mux_data->reg_umsk_isr); +} + +static void rtd1195_mux_enable_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux_data = irq_data_get_irq_chip_data(data); + unsigned long flags; + u32 mask; + + mask = mux_data->info->isr_to_int_en_mask[data->hwirq]; + if (!mask) + return; + + raw_spin_lock_irqsave(&mux_data->lock, flags); + + mux_data->scpu_int_en |= mask; + writel_relaxed(mux_data->scpu_int_en, mux_data->reg_scpu_int_en); + + raw_spin_unlock_irqrestore(&mux_data->lock, flags); +} + +static void rtd1195_mux_disable_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux_data = irq_data_get_irq_chip_data(data); + unsigned long flags; + u32 mask; + + mask = mux_data->info->isr_to_int_en_mask[data->hwirq]; + if (!mask) + return; + + raw_spin_lock_irqsave(&mux_data->lock, flags); + + mux_data->scpu_int_en &= ~mask; + writel_relaxed(mux_data->scpu_int_en, mux_data->reg_scpu_int_en); + + raw_spin_unlock_irqrestore(&mux_data->lock, flags); +} + +static struct irq_chip rtd1195_mux_irq_chip = { + .name = "rtd1195-mux", + .irq_mask = rtd1195_mux_mask_irq, + .irq_unmask = rtd1195_mux_unmask_irq, + .irq_enable = rtd1195_mux_enable_irq, + .irq_disable = rtd1195_mux_disable_irq, +}; + +static int rtd1195_mux_irq_domain_map(struct irq_domain *d, + unsigned int irq, irq_hw_number_t hw) +{ + struct rtd1195_irq_mux_data *data = d->host_data; + + irq_set_chip_and_handler(irq, &rtd1195_mux_irq_chip, handle_level_irq); + irq_set_chip_data(irq, data); + irq_set_probe(irq); + + return 0; +} + +static const struct irq_domain_ops rtd1195_mux_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = rtd1195_mux_irq_domain_map, +}; + +enum rtd1295_iso_isr_bits { + RTD1295_ISO_ISR_UR0_SHIFT = 2, + RTD1295_ISO_ISR_IRDA_SHIFT = 5, + RTD1295_ISO_ISR_I2C0_SHIFT = 8, + RTD1295_ISO_ISR_I2C1_SHIFT = 11, + RTD1295_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD1295_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD1295_ISO_ISR_GPIOA_SHIFT = 19, + RTD1295_ISO_ISR_GPIODA_SHIFT = 20, + RTD1295_ISO_ISR_GPHY_DV_SHIFT = 29, + RTD1295_ISO_ISR_GPHY_AV_SHIFT = 30, + RTD1295_ISO_ISR_I2C1_REQ_SHIFT = 31, +}; + +static const u32 rtd1295_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1295_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1295_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD1295_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1295_ISO_ISR_I2C1_SHIFT] = BIT(11), + [RTD1295_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD1295_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD1295_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1295_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1295_ISO_ISR_GPHY_DV_SHIFT] = BIT(29), + [RTD1295_ISO_ISR_GPHY_AV_SHIFT] = BIT(30), + [RTD1295_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31), +}; + +enum rtd1295_misc_isr_bits { + RTD1295_ISR_UR1_SHIFT = 3, + RTD1295_ISR_UR1_TO_SHIFT = 5, + RTD1295_ISR_UR2_SHIFT = 8, + RTD1295_ISR_RTC_MIN_SHIFT = 10, + RTD1295_ISR_RTC_HOUR_SHIFT = 11, + RTD1295_ISR_RTC_DATA_SHIFT = 12, + RTD1295_ISR_UR2_TO_SHIFT = 13, + RTD1295_ISR_I2C5_SHIFT = 14, + RTD1295_ISR_I2C4_SHIFT = 15, + RTD1295_ISR_GPIOA_SHIFT = 19, + RTD1295_ISR_GPIODA_SHIFT = 20, + RTD1295_ISR_LSADC0_SHIFT = 21, + RTD1295_ISR_LSADC1_SHIFT = 22, + RTD1295_ISR_I2C3_SHIFT = 23, + RTD1295_ISR_SC0_SHIFT = 24, + RTD1295_ISR_I2C2_SHIFT = 26, + RTD1295_ISR_GSPI_SHIFT = 27, + RTD1295_ISR_FAN_SHIFT = 29, +}; + +static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1295_ISR_UR1_SHIFT] = BIT(3), + [RTD1295_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD1295_ISR_UR2_TO_SHIFT] = BIT(6), + [RTD1295_ISR_UR2_SHIFT] = BIT(7), + [RTD1295_ISR_RTC_MIN_SHIFT] = BIT(10), + [RTD1295_ISR_RTC_HOUR_SHIFT] = BIT(11), + [RTD1295_ISR_RTC_DATA_SHIFT] = BIT(12), + [RTD1295_ISR_I2C5_SHIFT] = BIT(14), + [RTD1295_ISR_I2C4_SHIFT] = BIT(15), + [RTD1295_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1295_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1295_ISR_LSADC0_SHIFT] = BIT(21), + [RTD1295_ISR_LSADC1_SHIFT] = BIT(22), + [RTD1295_ISR_SC0_SHIFT] = BIT(24), + [RTD1295_ISR_I2C2_SHIFT] = BIT(26), + [RTD1295_ISR_GSPI_SHIFT] = BIT(27), + [RTD1295_ISR_I2C3_SHIFT] = BIT(28), + [RTD1295_ISR_FAN_SHIFT] = BIT(29), +}; + +static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask, +}; + +static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_int_en_mask = rtd1295_misc_isr_to_scpu_int_en_mask, +}; + +static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { + { + .compatible = "realtek,rtd1295-iso-irq-mux", + .data = &rtd1295_iso_irq_mux_info, + }, + { + .compatible = "realtek,rtd1295-misc-irq-mux", + .data = &rtd1295_misc_irq_mux_info, + }, + { + } +}; + +static int __init rtd1195_irq_mux_init(struct device_node *node, + struct device_node *parent) +{ + struct rtd1195_irq_mux_data *data; + const struct of_device_id *match; + const struct rtd1195_irq_mux_info *info; + void __iomem *base; + + match = of_match_node(rtd1295_irq_mux_dt_matches, node); + if (!match) + return -EINVAL; + + info = match->data; + if (!info) + return -EINVAL; + + base = of_iomap(node, 0); + if (!base) + return -EIO; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->info = info; + data->reg_isr = base + info->isr_offset; + data->reg_umsk_isr = base + info->umsk_isr_offset; + data->reg_scpu_int_en = base + info->scpu_int_en_offset; + + data->irq = irq_of_parse_and_map(node, 0); + if (data->irq <= 0) { + kfree(data); + return -EINVAL; + } + + raw_spin_lock_init(&data->lock); + + writel_relaxed(data->scpu_int_en, data->reg_scpu_int_en); + + data->domain = irq_domain_add_linear(node, 32, + &rtd1195_mux_irq_domain_ops, data); + if (!data->domain) { + kfree(data); + return -ENOMEM; + } + + irq_set_chained_handler_and_data(data->irq, rtd1195_mux_irq_handle, data); + + return 0; +} +IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init);

[v4,2/8] irqchip: Add Realtek RTD1295 mux driver

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