@@ -23,6 +23,8 @@
#ifndef GCC_AARCH_COMMON_PROTOS_H
#define GCC_AARCH_COMMON_PROTOS_H
+#include "hard-reg-set.h"
+
extern int aarch_accumulator_forwarding (rtx_insn *, rtx_insn *);
extern bool aarch_rev16_p (rtx);
extern bool aarch_rev16_shleft_mask_imm_p (rtx, machine_mode);
@@ -141,5 +143,9 @@ struct cpu_cost_table
const struct vector_cost_table vect;
};
+rtx_insn *
+arm_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/*inputs*/,
+ vec<const char *> &constraints,
+ vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs);
#endif /* GCC_AARCH_COMMON_PROTOS_H */
@@ -69,6 +69,8 @@ aarch64_define_unconditional_macros (cpp_reader *pfile)
builtin_define ("__ARM_FEATURE_UNALIGNED");
builtin_define ("__ARM_PCS_AAPCS64");
builtin_define_with_int_value ("__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE / 8);
+
+ builtin_define ("__GCC_ASM_FLAG_OUTPUTS__");
}
/* Undefine/redefine macros that depend on the current backend state and may
@@ -21947,6 +21947,9 @@ aarch64_libgcc_floating_mode_supported_p
#undef TARGET_STRICT_ARGUMENT_NAMING
#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
+#undef TARGET_MD_ASM_ADJUST
+#define TARGET_MD_ASM_ADJUST arm_md_asm_adjust
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-aarch64.h"
@@ -26,10 +26,16 @@
#include "config.h"
#include "system.h"
#include "coretypes.h"
+#include "insn-modes.h"
#include "tm.h"
#include "rtl.h"
#include "rtl-iter.h"
#include "memmodel.h"
+#include "errors.h"
+#include "tree.h"
+#include "expr.h"
+#include "function.h"
+#include "emit-rtl.h"
/* Return TRUE if X is either an arithmetic shift left, or
is a multiplication by a power of two. */
@@ -520,3 +526,128 @@ arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer)
&& !reg_overlap_mentioned_p (mul_result, mac_op0)
&& !reg_overlap_mentioned_p (mul_result, mac_op1));
}
+
+/* Worker function for TARGET_MD_ASM_ADJUST.
+ We implement asm flag outputs. */
+
+rtx_insn *
+arm_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/*inputs*/,
+ vec<const char *> &constraints,
+ vec<rtx> &/*clobbers*/, HARD_REG_SET &/*clobbered_regs*/)
+{
+ bool saw_asm_flag = false;
+
+ start_sequence ();
+ for (unsigned i = 0, n = outputs.length (); i < n; ++i)
+ {
+ const char *con = constraints[i];
+ if (strncmp (con, "=@cc", 4) != 0)
+ continue;
+ con += 4;
+ if (strchr (con, ',') != NULL)
+ {
+ error ("alternatives not allowed in %<asm%> flag output");
+ continue;
+ }
+
+ machine_mode mode = CCmode;
+ rtx_code code = UNKNOWN;
+
+ switch (con[0])
+ {
+ case 'c':
+ if (con[1] == 'c' && con[2] == 0)
+ mode = CC_Cmode, code = GEU;
+ else if (con[1] == 's' && con[2] == 0)
+ mode = CC_Cmode, code = LTU;
+ break;
+ case 'e':
+ if (con[1] == 'q' && con[2] == 0)
+ mode = CC_NZmode, code = EQ;
+ break;
+ case 'g':
+ if (con[1] == 'e' && con[2] == 0)
+ mode = CCmode, code = GE;
+ else if (con[1] == 't' && con[2] == 0)
+ mode = CCmode, code = GT;
+ break;
+ case 'h':
+ if (con[1] == 'i' && con[2] == 0)
+ mode = CCmode, code = GTU;
+ break;
+ case 'l':
+ if (con[1] == 'e' && con[2] == 0)
+ mode = CCmode, code = LE;
+ else if (con[1] == 't' && con[2] == 0)
+ mode = CCmode, code = LT;
+ else if (con[1] == 's' && con[2] == 0)
+ mode = CCmode, code = LEU;
+ break;
+ case 'm':
+ if (con[1] == 'i' && con[2] == 0)
+ mode = CC_NZmode, code = LT;
+ break;
+ case 'n':
+ if (con[1] == 'e' && con[2] == 0)
+ mode = CC_NZmode, code = NE;
+ break;
+ case 'p':
+ if (con[1] == 'l' && con[2] == 0)
+ mode = CC_NZmode, code = GE;
+ break;
+ case 'v':
+ if (con[1] == 'c' && con[2] == 0)
+ mode = CC_Vmode, code = EQ;
+ else if (con[1] == 's' && con[2] == 0)
+ mode = CC_Vmode, code = NE;
+ break;
+ }
+ if (code == UNKNOWN)
+ {
+ error ("unknown %<asm%> flag output %qs", constraints[i]);
+ continue;
+ }
+
+ rtx dest = outputs[i];
+ machine_mode dest_mode = GET_MODE (dest);
+ if (!SCALAR_INT_MODE_P (dest_mode))
+ {
+ error ("invalid type for %<asm%> flag output");
+ continue;
+ }
+
+ if (!saw_asm_flag)
+ {
+ /* This is the first asm flag output. Here we put the flags
+ register in as the real output and adjust the condition to
+ allow it. */
+ constraints[i] = "=c";
+ outputs[i] = gen_rtx_REG (CCmode, CC_REGNUM);
+ saw_asm_flag = true;
+ }
+ else
+ {
+ /* We don't need the flags register as output twice. */
+ constraints[i] = "=X";
+ outputs[i] = gen_rtx_SCRATCH (word_mode);
+ }
+
+ rtx x = gen_rtx_REG (mode, CC_REGNUM);
+ x = gen_rtx_fmt_ee (code, word_mode, x, const0_rtx);
+
+ if (dest_mode == word_mode)
+ emit_insn (gen_rtx_SET (dest, x));
+ else
+ {
+ rtx tmp = gen_reg_rtx (word_mode);
+ emit_insn (gen_rtx_SET (tmp, x));
+
+ tmp = convert_modes (dest_mode, word_mode, tmp, true);
+ emit_move_insn (dest, tmp);
+ }
+ }
+ rtx_insn *seq = get_insns ();
+ end_sequence ();
+
+ return saw_asm_flag ? seq : NULL;
+}
@@ -122,6 +122,7 @@ arm_cpu_builtins (struct cpp_reader* pfile)
if (arm_arch_notm)
builtin_define ("__ARM_ARCH_ISA_ARM");
builtin_define ("__APCS_32__");
+ builtin_define ("__GCC_ASM_FLAG_OUTPUTS__");
def_or_undef_macro (pfile, "__thumb__", TARGET_THUMB);
def_or_undef_macro (pfile, "__thumb2__", TARGET_THUMB2);
@@ -814,6 +814,9 @@ static const struct attribute_spec arm_attribute_table[] =
#undef TARGET_CONSTANT_ALIGNMENT
#define TARGET_CONSTANT_ALIGNMENT arm_constant_alignment
+
+#undef TARGET_MD_ASM_ADJUST
+#define TARGET_MD_ASM_ADJUST arm_md_asm_adjust
/* Obstack for minipool constant handling. */
static struct obstack minipool_obstack;
@@ -9771,6 +9771,39 @@ referenced within the assembler template via @code{%0} etc, as there's
no corresponding text in the assembly language.
@table @asis
+@item ARM
+@itemx AArch64
+The flag output constraints for the ARM family are of the form
+@samp{=@@cc@var{cond}} where @var{cond} is one of the standard
+conditions defined in the ARM ARM for @code{ConditionHolds}.
+
+@table @code
+@item eq
+``equal'' or Z flag set
+@item ne
+``not equal'' or Z flag clear
+@item cs
+``carry'' or C flag set
+@item cc
+C flag clear
+@item mi
+``minus'' or N flag set
+@item pl
+``plus'' or N flag clear
+@item hi
+unsigned greater than
+@item ls
+unsigned less than or equal
+@item ge
+signed greater than or equal
+@item lt
+signed less than
+@item gt
+signed greater than
+@item le
+signed less than or equal
+@end table
+
@item x86 family
The flag output constraints for the x86 family are of the form
@samp{=@@cc@var{cond}} where @var{cond} is one of the standard