[07/29,arm] Remove redundant DImode subtract patterns

Message ID	20191018194900.34795-8-Richard.Earnshaw@arm.com
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of gcc-patches-return-511337-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=ZOvKA7jtvfdLRP1S qUSFim0a3EUbqY8bvxG+y7qAxsYOPZrbdaLBr8DuUDh7lFCaRbn5Zkiw0ntYG0pf uiBI20XdKohTeZ1hTtwoTY/PxuBj41te8gBLE1uDOFn0TNtYpCqhp5c1uaVDqGyy D0OU2B7r2MBcx/E/v38BEwmX8Vg= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: Richard Earnshaw <Richard.Earnshaw@arm.com> To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw <Richard.Earnshaw@arm.com> Subject: [PATCH 07/29] [arm] Remove redundant DImode subtract patterns Date: Fri, 18 Oct 2019 20:48:38 +0100 Message-Id: <20191018194900.34795-8-Richard.Earnshaw@arm.com> In-Reply-To: <20191018194900.34795-1-Richard.Earnshaw@arm.com> References: <20191018194900.34795-1-Richard.Earnshaw@arm.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------2.17.1"
Series	Rewrite DImode arithmetic support \| expand [00/29,arm] Rewrite DImode arithmetic support [01/29,arm] Rip out DImode addition and subtraction splits. [02/29,arm] Perform early splitting of adddi3. [03/29,arm] Early split zero- and sign-extension [04/29,arm] Rewrite addsi3_carryin_shift_<optab> in canonical form [05/29,arm] fix constraints on addsi3_carryin_alt2 [06/29,arm] Early split subdi3 [07/29,arm] Remove redundant DImode subtract patterns [08/29,arm] Introduce arm_carry_operation [09/29,arm] Correctly cost addition with a carry-in [10/29,arm] Correct cost calculations involving borrow for subtracts. [11/29,arm] Reduce cost of insns that are simple reg-reg moves. [12/29,arm] Implement negscc using SBC when appropriate. [13/29,arm] Add alternative canonicalizations for subtract-with-carry + shift [14/29,arm] Early split simple DImode equality comparisons [15/29,arm] Improve handling of DImode comparisions against constants. [16/29,arm] early split most DImode comparison operations. [17/29,arm] Handle some constant comparisons using rsbs+rscs [18/29,arm] Cleanup dead code - old support for DImode comparisons [19/29,arm] Handle immediate values in uaddvsi4 [20/29,arm] Early expansion of uaddvdi4. [21/29,arm] Improve code generation for addvsi4. [22/29,arm] Allow the summation result of signed add-with-overflow to be discarded. [23/29,arm] Early split addvdi4 [24/29,arm] Improve constant handling for usubvsi4. [25/29,arm] Early expansion of usubvdi4. [26/29,arm] Improve constant handling for subvsi4. [27/29,arm] Early expansion of subvdi4 [28/29,arm] Improvements to negvsi4 and negvdi4. [29/29,arm] Fix testsuite nit when compiling for thumb2

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From: Richard Earnshaw <Richard.Earnshaw@arm.com>
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Subject: [PATCH 07/29] [arm] Remove redundant DImode subtract patterns
Date: Fri, 18 Oct 2019 20:48:38 +0100
Message-Id: <20191018194900.34795-8-Richard.Earnshaw@arm.com>
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Series

Rewrite DImode arithmetic support | expand

Commit Message

Richard Earnshaw (lists) Oct. 18, 2019, 7:48 p.m. UTC

Now that we early split DImode subtracts, the patterns to emit the
original and to match zero-extend with subtraction or negation are
no-longer useful.

	* config/arm/arm.md (arm_subdi3): Delete insn.
	(zextendsidi_negsi, negdi_extendsidi): Delete insn_and_split.
---
 gcc/config/arm/arm.md | 102 ------------------------------------------
 1 file changed, 102 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 99d931525f8..f597a277c17 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1161,18 +1161,6 @@  (define_expand "subdi3"
   "
 )
 
-(define_insn "*arm_subdi3"
-  [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r,&r")
-	(minus:DI (match_operand:DI 1 "arm_general_register_operand" "0,r,0")
-		  (match_operand:DI 2 "arm_general_register_operand" "r,0,0")))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_32BIT"
-  "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"
-  [(set_attr "conds" "clob")
-   (set_attr "length" "8")
-   (set_attr "type" "multiple")]
-)
-
 (define_expand "subsi3"
   [(set (match_operand:SI           0 "s_register_operand")
 	(minus:SI (match_operand:SI 1 "reg_or_int_operand")
@@ -3866,96 +3854,6 @@  (define_expand "negdf2"
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
   "")
 
-(define_insn_and_split "*zextendsidi_negsi"
-  [(set (match_operand:DI 0 "s_register_operand" "=r")
-        (zero_extend:DI (neg:SI (match_operand:SI 1 "s_register_operand" "r"))))]
-   "TARGET_32BIT"
-   "#"
-   ""
-   [(set (match_dup 2)
-         (neg:SI (match_dup 1)))
-    (set (match_dup 3)
-         (const_int 0))]
-   {
-      operands[2] = gen_lowpart (SImode, operands[0]);
-      operands[3] = gen_highpart (SImode, operands[0]);
-   }
- [(set_attr "length" "8")
-  (set_attr "type" "multiple")]
-)
-
-;; Negate an extended 32-bit value.
-(define_insn_and_split "*negdi_extendsidi"
-  [(set (match_operand:DI 0 "s_register_operand" "=l,r")
-	(neg:DI (sign_extend:DI
-		 (match_operand:SI 1 "s_register_operand" "l,r"))))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_32BIT"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-  {
-    rtx low = gen_lowpart (SImode, operands[0]);
-    rtx high = gen_highpart (SImode, operands[0]);
-
-    if (reg_overlap_mentioned_p (low, operands[1]))
-      {
-	/* Input overlaps the low word of the output.  Use:
-		asr	Rhi, Rin, #31
-		rsbs	Rlo, Rin, #0
-		rsc	Rhi, Rhi, #0 (thumb2: sbc Rhi, Rhi, Rhi, lsl #1).  */
-	rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
-
-	emit_insn (gen_rtx_SET (high,
-				gen_rtx_ASHIFTRT (SImode, operands[1],
-						  GEN_INT (31))));
-
-	emit_insn (gen_subsi3_compare (low, const0_rtx, operands[1]));
-	if (TARGET_ARM)
-	  emit_insn (gen_rtx_SET (high,
-				  gen_rtx_MINUS (SImode,
-						 gen_rtx_MINUS (SImode,
-								const0_rtx,
-								high),
-						 gen_rtx_LTU (SImode,
-							      cc_reg,
-							      const0_rtx))));
-	else
-	  {
-	    rtx two_x = gen_rtx_ASHIFT (SImode, high, GEN_INT (1));
-	    emit_insn (gen_rtx_SET (high,
-				    gen_rtx_MINUS (SImode,
-						   gen_rtx_MINUS (SImode,
-								  high,
-								  two_x),
-						   gen_rtx_LTU (SImode,
-								cc_reg,
-								const0_rtx))));
-	  }
-      }
-    else
-      {
-	/* No overlap, or overlap on high word.  Use:
-		rsb	Rlo, Rin, #0
-		bic	Rhi, Rlo, Rin
-		asr	Rhi, Rhi, #31
-	   Flags not needed for this sequence.  */
-	emit_insn (gen_rtx_SET (low, gen_rtx_NEG (SImode, operands[1])));
-	emit_insn (gen_rtx_SET (high,
-				gen_rtx_AND (SImode,
-					     gen_rtx_NOT (SImode, operands[1]),
-					     low)));
-	emit_insn (gen_rtx_SET (high,
-				gen_rtx_ASHIFTRT (SImode, high,
-						  GEN_INT (31))));
-      }
-    DONE;
-  }
-  [(set_attr "length" "12")
-   (set_attr "arch" "t2,*")
-   (set_attr "type" "multiple")]
-)
-
 ;; abssi2 doesn't really clobber the condition codes if a different register
 ;; is being set.  To keep things simple, assume during rtl manipulations that
 ;; it does, but tell the final scan operator the truth.  Similarly for

[07/29,arm] Remove redundant DImode subtract patterns

Commit Message

Patch