| Message ID | 20191011134744.2477-15-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v5,01/22] target/arm: Add MTE_ACTIVE to tb_flags | expand |
On Fri, 11 Oct 2019 at 14:50, Richard Henderson <richard.henderson@linaro.org> wrote: > > Like the regular data cache flushes, these are nops within qemu. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/helper.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index f435a8d8bd..33bc176e1c 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -5978,6 +5978,54 @@ static const ARMCPRegInfo mte_reginfo[] = { > { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, > .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, > + { .name = "IGVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "IGSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "IGDVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "IGDSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGDSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CIGSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CIGDSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGDVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGVAP", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGDVAP", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGVADP", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CGDVADP", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CIGVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, > + .type = ARM_CP_NOP, .access = PL1_W }, > + { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, > + .type = ARM_CP_NOP, .access = PL1_W }, > REGINFO_SENTINEL > }; Some of these, but not all, are conditionally available at EL0, which means that for those that are: * .access should be PL0_W * .accessfn should be aa64_cacheop_access() (which checks SCTLR_EL1.UCI) * they need to be in a reginfo that makes them available for the insns-and-regs-only flavour of MTE thanks -- PMM
diff --git a/target/arm/helper.c b/target/arm/helper.c index f435a8d8bd..33bc176e1c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5978,6 +5978,54 @@ static const ARMCPRegInfo mte_reginfo[] = { { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, + { .name = "IGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, REGINFO_SENTINEL };
Like the regular data cache flushes, these are nops within qemu. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/helper.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.1