| Message ID | 20190911164959.11003-4-alex.bennee@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | semihosting cleanups (plus minor tests/tcg tweak) | expand |
On Wed, 11 Sep 2019 at 17:50, Alex Bennée <alex.bennee@linaro.org> wrote: > > As for the other semihosting calls we can resolve this at translate > time. > > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > > --- > v2 > - update for change to gen_exception_internal_insn API > v3 > - update for decode tree, merge T32 & A32 commits > - dropped r-b due to changes > v4 > - !IS_USER and !arm_dc_feature(s, ARM_FEATURE_M) > v5 > - only if !IS_USER for softmmu, linux-user is still allowed > --- > target/arm/translate.c | 19 +++++++++++++++---- > 1 file changed, 15 insertions(+), 4 deletions(-) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 6689acc911e..fac791c4b06 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -10219,14 +10219,25 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a) > } > > /* > - * Supervisor call > + * Supervisor call - both T32 & A32 come here so we need to check > + * which mode we are in when checking for semihosting. > */ > > static bool trans_SVC(DisasContext *s, arg_SVC *a) > { > - gen_set_pc_im(s, s->base.pc_next); > - s->svc_imm = a->imm; > - s->base.is_jmp = DISAS_SWI; > + const uint32_t semihost_imm = s->thumb ? 0xab : 0x123456; > + > + if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() && > +#ifndef CONFIG_USER_ONLY > + !IS_USER(s) && > +#endif > + (a->imm == semihost_imm)) { > + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); > + } else { > + gen_set_pc_im(s, s->base.pc_next); > + s->svc_imm = a->imm; > + s->base.is_jmp = DISAS_SWI; > + } > return true; > } Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/translate.c b/target/arm/translate.c index 6689acc911e..fac791c4b06 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10219,14 +10219,25 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a) } /* - * Supervisor call + * Supervisor call - both T32 & A32 come here so we need to check + * which mode we are in when checking for semihosting. */ static bool trans_SVC(DisasContext *s, arg_SVC *a) { - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm = a->imm; - s->base.is_jmp = DISAS_SWI; + const uint32_t semihost_imm = s->thumb ? 0xab : 0x123456; + + if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + !IS_USER(s) && +#endif + (a->imm == semihost_imm)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + } else { + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm = a->imm; + s->base.is_jmp = DISAS_SWI; + } return true; }
As for the other semihosting calls we can resolve this at translate time. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> --- v2 - update for change to gen_exception_internal_insn API v3 - update for decode tree, merge T32 & A32 commits - dropped r-b due to changes v4 - !IS_USER and !arm_dc_feature(s, ARM_FEATURE_M) v5 - only if !IS_USER for softmmu, linux-user is still allowed --- target/arm/translate.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) -- 2.20.1