@@ -3518,10 +3518,29 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
}
+static void update_el2_asid(CPUARMState *env)
+{
+ CPUState *cs = env_cpu(env);
+ uint64_t ttbr0, ttbr1, ttcr;
+ int asid, idxmask;
+
+ ttbr0 = env->cp15.ttbr0_el[2];
+ ttbr1 = env->cp15.ttbr1_el[2];
+ ttcr = env->cp15.tcr_el[2].raw_tcr;
+ idxmask = ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0;
+ asid = extract64(ttcr & TTBCR_A1 ? ttbr1 : ttbr0, 48, 16);
+
+ tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0);
+}
+
static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
raw_write(env, ri, value);
+ if (arm_hcr_el2_eff(env) & HCR_E2H) {
+ /* We are running with EL2&0 regime and the ASID is active. */
+ update_el2_asid(env);
+ }
}
static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4670,6 +4689,7 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
ARMCPU *cpu = env_archcpu(env);
/* Begin with bits defined in base ARMv8.0. */
uint64_t valid_mask = MAKE_64BIT_MASK(0, 34);
+ uint64_t old_value;
if (arm_feature(env, ARM_FEATURE_EL3)) {
valid_mask &= ~HCR_HCD;
@@ -4696,15 +4716,25 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
/* Clear RES0 bits. */
value &= valid_mask;
- /* These bits change the MMU setup:
+ old_value = env->cp15.hcr_el2;
+ env->cp15.hcr_el2 = value;
+
+ /*
+ * These bits change the MMU setup:
* HCR_VM enables stage 2 translation
* HCR_PTW forbids certain page-table setups
- * HCR_DC Disables stage1 and enables stage2 translation
+ * HCR_DC disables stage1 and enables stage2 translation
+ * HCR_E2H enables E2&0 translation regime.
*/
- if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
+ if ((old_value ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_E2H)) {
tlb_flush(CPU(cpu));
+ /* Also install the correct ASID for the regime. */
+ if (value & HCR_E2H) {
+ update_el2_asid(env);
+ } else {
+ update_lpae_el1_asid(env, false);
+ }
}
- env->cp15.hcr_el2 = value;
/*
* Updates to VI and VF require us to update the status of
When clearing HCR_E2H, this involves re-installing the EL1&0 asid. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/helper.c | 38 ++++++++++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) -- 2.17.1