@@ -2850,8 +2850,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
#define ARM_MMU_IDX_COREIDX_MASK 0x7
typedef enum ARMMMUIdx {
- ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A,
- ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A,
+ ARMMMUIdx_EL10_0 = 0 | ARM_MMU_IDX_A,
+ ARMMMUIdx_EL10_1 = 1 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
@@ -2876,8 +2876,8 @@ typedef enum ARMMMUIdx {
* for use when calling tlb_flush_by_mmuidx() and friends.
*/
typedef enum ARMMMUIdxBit {
- ARMMMUIdxBit_S12NSE0 = 1 << 0,
- ARMMMUIdxBit_S12NSE1 = 1 << 1,
+ ARMMMUIdxBit_EL10_0 = 1 << 0,
+ ARMMMUIdxBit_EL10_1 = 1 << 1,
ARMMMUIdxBit_S1E2 = 1 << 2,
ARMMMUIdxBit_S1E3 = 1 << 3,
ARMMMUIdxBit_S1SE0 = 1 << 4,
@@ -808,8 +808,8 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu)
static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
- case ARMMMUIdx_S12NSE0:
- case ARMMMUIdx_S12NSE1:
+ case ARMMMUIdx_EL10_0:
+ case ARMMMUIdx_EL10_1:
case ARMMMUIdx_S1NSE0:
case ARMMMUIdx_S1NSE1:
case ARMMMUIdx_S1E2:
@@ -569,7 +569,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
idxmask = ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
break;
case ARM_CP_SECSTATE_NS:
- idxmask = ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
+ idxmask = ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0;
break;
default:
g_assert_not_reached();
@@ -682,8 +682,8 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
+ ARMMMUIdxBit_EL10_1 |
+ ARMMMUIdxBit_EL10_0 |
ARMMMUIdxBit_S2NS);
}
@@ -693,8 +693,8 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
+ ARMMMUIdxBit_EL10_1 |
+ ARMMMUIdxBit_EL10_0 |
ARMMMUIdxBit_S2NS);
}
@@ -3047,7 +3047,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
if (arm_feature(env, ARM_FEATURE_EL2)) {
- if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
+ if (mmu_idx == ARMMMUIdx_EL10_0 || mmu_idx == ARMMMUIdx_EL10_1) {
format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
} else {
format64 |= arm_current_el(env) == 2;
@@ -3146,11 +3146,11 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
break;
case 4:
/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
- mmu_idx = ARMMMUIdx_S12NSE1;
+ mmu_idx = ARMMMUIdx_EL10_1;
break;
case 6:
/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
- mmu_idx = ARMMMUIdx_S12NSE0;
+ mmu_idx = ARMMMUIdx_EL10_0;
break;
default:
g_assert_not_reached();
@@ -3208,10 +3208,10 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
break;
case 4: /* AT S12E1R, AT S12E1W */
- mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
+ mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1;
break;
case 6: /* AT S12E0R, AT S12E0W */
- mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
+ mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_EL10_0;
break;
default:
g_assert_not_reached();
@@ -3430,7 +3430,7 @@ static void update_lpae_el1_asid(CPUARMState *env, int secure)
ttbr0 = env->cp15.ttbr0_ns;
ttbr1 = env->cp15.ttbr1_ns;
ttcr = env->cp15.tcr_el[1].raw_tcr;
- idxmask = ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
+ idxmask = ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0;
break;
default:
g_assert_not_reached();
@@ -3540,10 +3540,10 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
/*
* A change in VMID to the stage2 page table (S2NS) invalidates
- * the combined stage 1&2 tlbs (S12NSE1 and S12NSE0).
+ * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
*/
tlb_set_asid_for_mmuidx(cs, vmid, ARMMMUIdxBit_S2NS,
- ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0);
+ ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0);
}
static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
@@ -3901,7 +3901,7 @@ static int vae1_tlbmask(CPUARMState *env)
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
} else {
- return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
+ return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0;
}
}
@@ -3937,9 +3937,9 @@ static int vmalle1_tlbmask(CPUARMState *env)
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
} else if (arm_feature(env, ARM_FEATURE_EL2)) {
- return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_S2NS;
+ return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_S2NS;
} else {
- return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
+ return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0;
}
}
@@ -8801,8 +8801,8 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
*/
static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
{
- if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
- mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0);
+ if (mmu_idx == ARMMMUIdx_EL10_0 || mmu_idx == ARMMMUIdx_EL10_1) {
+ mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_EL10_0);
}
return mmu_idx;
}
@@ -8845,8 +8845,8 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
return true;
default:
return false;
- case ARMMMUIdx_S12NSE0:
- case ARMMMUIdx_S12NSE1:
+ case ARMMMUIdx_EL10_0:
+ case ARMMMUIdx_EL10_1:
g_assert_not_reached();
}
}
@@ -10750,7 +10750,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
target_ulong *page_size,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
{
- if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
+ if (mmu_idx == ARMMMUIdx_EL10_0 || mmu_idx == ARMMMUIdx_EL10_1) {
/* Call ourselves recursively to do the stage 1 and then stage 2
* translations.
*/
@@ -11281,7 +11281,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
if (el < 2 && arm_is_secure_below_el3(env)) {
return ARMMMUIdx_S1SE0 + el;
} else {
- return ARMMMUIdx_S12NSE0 + el;
+ return ARMMMUIdx_EL10_0 + el;
}
}
@@ -113,8 +113,8 @@ static inline int get_a64_user_mem_index(DisasContext *s)
ARMMMUIdx useridx;
switch (s->mmu_idx) {
- case ARMMMUIdx_S12NSE1:
- useridx = ARMMMUIdx_S12NSE0;
+ case ARMMMUIdx_EL10_1:
+ useridx = ARMMMUIdx_EL10_0;
break;
case ARMMMUIdx_S1SE1:
useridx = ARMMMUIdx_S1SE0;
@@ -153,9 +153,9 @@ static inline int get_a32_user_mem_index(DisasContext *s)
*/
switch (s->mmu_idx) {
case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */
- case ARMMMUIdx_S12NSE0:
- case ARMMMUIdx_S12NSE1:
- return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0);
+ case ARMMMUIdx_EL10_0:
+ case ARMMMUIdx_EL10_1:
+ return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0);
case ARMMMUIdx_S1E3:
case ARMMMUIdx_S1SE0:
case ARMMMUIdx_S1SE1:
This is part of a reorganization to the set of mmu_idx. This emphasizes that they apply to the EL1&0 regime. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 8 +++---- target/arm/internals.h | 4 ++-- target/arm/helper.c | 44 +++++++++++++++++++------------------- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 6 +++--- 5 files changed, 33 insertions(+), 33 deletions(-) -- 2.17.1