Message ID | 5c9020bc.1c69fb81.6977e.d27a@mx.google.com |
---|---|
State | New |
Headers | show |
Series | ulfh/next boot bisection: v5.1-rc1-22-gb3725d97ba75 on rk3399-gru-kevin | expand |
On Tue, 19 Mar 2019 at 01:38, Shawn Lin <shawn.lin@rock-chips.com> wrote: > > > On 2019/3/19 6:50, kernelci.org bot wrote: > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * > > * This automated bisection report was sent to you on the basis * > > * that you may be involved with the breaking commit it has * > > * found. No manual investigation has been done to verify it, * > > * and the root cause of the problem may be somewhere else. * > > * Hope this helps! * > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * > > > > ulfh/next boot bisection: v5.1-rc1-22-gb3725d97ba75 on rk3399-gru-kevin > > > > Summary: > > Start: b3725d97ba75 Merge branch 'fixes' into next > > Details: https://kernelci.org/boot/id/5c8fa85d59b5148afcfe6052 > > Plain log: https://storage.kernelci.org//ulfh/next/v5.1-rc1-22-gb3725d97ba75/arm64/defconfig/gcc-7/lab-collabora/boot-rk3399-gru-kevin.txt > > HTML log: https://storage.kernelci.org//ulfh/next/v5.1-rc1-22-gb3725d97ba75/arm64/defconfig/gcc-7/lab-collabora/boot-rk3399-gru-kevin.html > > Result: d6a6d722481f mmc: dw_mmc-rockchip: Enable hardware unbusy interrupt support > > Thanks for report! > > Ulf, > > It's a known issue already but didn't got managed to post v3 due to > weekend. Should I post a increamental patch on top? or just resend a > v3 series? I have just dropped the offending patches (the series), please post a new version. [...] Kind regards Uffe
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index 8c86a800a8fd..85b1e42782a0 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -20,6 +20,9 @@ #include "dw_mmc-pltfm.h" #define RK3288_CLKGEN_DIV 2 +#define RKMMC_RDYINT_GEN 0x120 +#define RKMMC_RDYINT_GEN_WORKING BIT(8) +#define RKMMC_RDYINT_GEN_MAXVAL GENMASK(7, 0) struct dw_mci_rockchip_priv_data { struct clk *drv_clk; @@ -28,6 +31,23 @@ struct dw_mci_rockchip_priv_data { int num_phases; }; +static int dw_mci_rockchip_prepare_hw_unbusy(struct dw_mci *host, + bool enable) +{ + u32 reg = readl(host->regs + RKMMC_RDYINT_GEN); + + if (enable) + /* Self-clean when generating unbusy int */ + reg |= RKMMC_RDYINT_GEN_WORKING; + else + /* Otherwise do it manually to avoid racing condition */ + reg &= ~RKMMC_RDYINT_GEN_WORKING; + + writel(reg, host->regs + RKMMC_RDYINT_GEN); + + return 0; +} + static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) { struct dw_mci_rockchip_priv_data *priv = host->priv; @@ -301,6 +321,15 @@ static int dw_mci_rockchip_init(struct dw_mci *host) "rockchip,rk3288-dw-mshc")) host->bus_hz /= RK3288_CLKGEN_DIV; + /* Some Rockchip SoCs use hw unbusy int */ + if (of_device_is_compatible(host->dev->of_node, + "rockchip,rk1808-dw-mshc")) { + host->hw_unbusy_int = 16; + writel(~(RKMMC_RDYINT_GEN_WORKING | + RKMMC_RDYINT_GEN_MAXVAL), + host->regs + RKMMC_RDYINT_GEN); + } + return 0; } @@ -322,6 +351,7 @@ static const struct dw_mci_drv_data rk3288_drv_data = { .set_ios = dw_mci_rk3288_set_ios, .execute_tuning = dw_mci_rk3288_execute_tuning, .parse_dt = dw_mci_rk3288_parse_dt, + .prepare_hw_unbusy = dw_mci_rockchip_prepare_hw_unbusy, .init = dw_mci_rockchip_init, }; -------------------------------------------------------------------------------