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[v2,1/3] dt-bindings: ufs: Add HI3670 UFS controller binding

Message ID 20190105072859.9134-2-manivannan.sadhasivam@linaro.org
State Accepted
Commit cc8ed1a9d65c537742b40658d94e0ebea9cb0e81
Headers show
Series [v2,1/3] dt-bindings: ufs: Add HI3670 UFS controller binding | expand

Commit Message

Manivannan Sadhasivam Jan. 5, 2019, 7:28 a.m. UTC
Add devicetree binding for HI3670 UFS controller. HI3760 SoC is very
similar to HI3660 SoC with almost same IPs. Only major difference in terms
of UFS is the PHY. HI3670 has 10nm PHY. But since the original driver
(HI3660 UFS) cannot make HI3670 UFS functional, a separate compatible
is added for HI3670 without any fallback.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

---
 Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

-- 
2.17.1
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Patch

diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
index a48c44817367..0b83df1a5418 100644
--- a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
+++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
@@ -6,9 +6,10 @@  Each UFS Host Controller should have its own node.
 Required properties:
 - compatible        : compatible list, contains one of the following -
 					"hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
-					host controller present on Hi36xx chipset.
+					host controller present on Hi3660 chipset.
+					"hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs
+					host controller present on Hi3670 chipset.
 - reg               : should contain UFS register address space & UFS SYS CTRL register address,
-- interrupt-parent  : interrupt device
 - interrupts        : interrupt number
 - clocks	        : List of phandle and clock specifier pairs
 - clock-names       : List of clock input name strings sorted in the same