@@ -41,7 +41,7 @@
#define LTSSM_STATE_MASK 0x1f
#define LTSSM_STATE_L0 0x11
#define DBI_CS2_EN_VAL 0x20
-#define OB_XLAT_EN_VAL 2
+#define OB_XLAT_EN_VAL BIT(1)
/* Application registers */
#define CMD_STATUS 0x004
@@ -53,11 +53,10 @@
#define CFG_TYPE1 BIT(24)
#define OB_SIZE 0x030
-#define CFG_PCIM_WIN_SZ_IDX 3
-#define CFG_PCIM_WIN_CNT 32
#define SPACE0_REMOTE_CFG_OFFSET 0x1000
#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n)))
#define OB_OFFSET_HI(n) (0x204 + (8 * (n)))
+#define OB_WIN_SIZE 8 /* 8MB */
/* IRQ register defines */
#define IRQ_EOI 0x050
@@ -87,6 +86,11 @@
#define ERR_IRQ_ENABLE_SET 0x1c8
#define ERR_IRQ_ENABLE_CLR 0x1cc
+#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n)))
+#define OB_ENABLEN BIT(0)
+
+#define OB_OFFSET_HI(n) (0x204 + (8 * (n)))
+
/* Config space registers */
#define DEBUG0 0x728
@@ -111,6 +115,7 @@ struct keystone_pcie {
int num_msi_host_irqs;
int msi_host_irqs[MAX_MSI_HOST_IRQS];
int num_lanes;
+ u32 num_viewport;
struct phy **phy;
struct device_link **link;
struct device_node *msi_intc_np;
@@ -341,11 +346,13 @@ static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
{
+ u32 val;
+ u32 num_viewport = ks_pcie->num_viewport;
struct dw_pcie *pci = ks_pcie->pci;
struct pcie_port *pp = &pci->pp;
- u32 start = pp->mem->start, end = pp->mem->end;
- int i, tr_size;
- u32 val;
+ u64 start = pp->mem->start;
+ u64 end = pp->mem->end;
+ int i;
/* Disable BARs for inbound access */
ks_pcie_set_dbi_mode(ks_pcie);
@@ -353,21 +360,21 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
ks_pcie_clear_dbi_mode(ks_pcie);
- /* Set outbound translation size per window division */
- ks_pcie_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
-
- tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
+ val = ilog2(OB_WIN_SIZE);
+ ks_pcie_app_writel(ks_pcie, OB_SIZE, val);
/* Using Direct 1:1 mapping of RC <-> PCI memory space */
- for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
- ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
- ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
- start += tr_size;
+ for (i = 0; i < num_viewport && (start < end); i++) {
+ ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i),
+ lower_32_bits(start) | OB_ENABLEN);
+ ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i),
+ upper_32_bits(start));
+ start += OB_WIN_SIZE;
}
- /* Enable OB translation */
val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
- ks_pcie_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
+ val |= OB_XLAT_EN_VAL;
+ ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
}
static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
@@ -902,6 +909,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
struct dw_pcie *pci;
struct keystone_pcie *ks_pcie;
struct device_link **link;
+ u32 num_viewport;
struct phy **phy;
u32 num_lanes;
char name[10];
@@ -919,6 +927,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
pci->dev = dev;
pci->ops = &ks_pcie_dw_pcie_ops;
+ ret = of_property_read_u32(np, "num-viewport", &num_viewport);
+ if (ret < 0) {
+ dev_err(dev, "unable to read *num-viewport* property\n");
+ return ret;
+ }
+
ret = of_property_read_u32(np, "num-lanes", &num_lanes);
if (ret)
num_lanes = 1;
@@ -953,6 +967,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
ks_pcie->pci = pci;
ks_pcie->link = link;
ks_pcie->num_lanes = num_lanes;
+ ks_pcie->num_viewport = num_viewport;
ks_pcie->phy = phy;
ret = ks_pcie_enable_phy(ks_pcie);
Instead of having a fixed outbound window count, get the number of outbound windows from device tree. Also cleanup memory space configuration here by adding macros for constants. While at that also use BIT() macro for OB_XLAT_EN_VAL. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- drivers/pci/controller/dwc/pci-keystone.c | 47 +++++++++++++++-------- 1 file changed, 31 insertions(+), 16 deletions(-) -- 2.17.1