diff mbox series

[v3,2/3] arm: Add Nordic Semiconductor nRF51 SoC

Message ID 20180726023645.13927-3-joel@jms.id.au
State Superseded
Headers show
Series arm: Add nRF51 SoC and micro:bit machine | expand

Commit Message

Joel Stanley July 26, 2018, 2:36 a.m. UTC 
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module,
plus other common ARM SoC peripherals.

 http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf

This defines a basic model of the CPU and memory, with no peripherals
implemented at this stage.

Signed-off-by: Joel Stanley <joel@jms.id.au>

---
v2:
  put memory as struct fileds in state structure
  pass OBJECT(s) as owner, not NULL
  Add missing addresses for ficr
  Fix flash and sram sizes for microbit
  Embed cpu object in state object an initalise it without use of armv7m_init
  Link to datasheet
v3:
  rebase nrf51 on m0 changes
  remove unused kernel_filename
  clarify flash and sram size
  make flash and sram size properties of the soc state
---
 default-configs/arm-softmmu.mak |   1 +
 hw/arm/Makefile.objs            |   1 +
 hw/arm/nrf51_soc.c              | 119 ++++++++++++++++++++++++++++++++
 include/hw/arm/nrf51_soc.h      |  42 +++++++++++
 4 files changed, 163 insertions(+)
 create mode 100644 hw/arm/nrf51_soc.c
 create mode 100644 include/hw/arm/nrf51_soc.h

-- 
2.17.1

Comments

Xingtao Yao (Fujitsu)" via July 26, 2018, 11:01 a.m. UTC | #1 
On 26.07.2018 05:36, Joel Stanley wrote:
> The nRF51 is a Cortex-M0 microcontroller with an on-board radio module,

> plus other common ARM SoC peripherals.

> 

>   http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf

> 

> This defines a basic model of the CPU and memory, with no peripherals

> implemented at this stage.

> 

> Signed-off-by: Joel Stanley <joel@jms.id.au>

> ---

> v2:

>    put memory as struct fileds in state structure

>    pass OBJECT(s) as owner, not NULL

>    Add missing addresses for ficr

>    Fix flash and sram sizes for microbit

>    Embed cpu object in state object an initalise it without use of armv7m_init

>    Link to datasheet

> v3:

>    rebase nrf51 on m0 changes

>    remove unused kernel_filename

>    clarify flash and sram size

>    make flash and sram size properties of the soc state

> ---

>   default-configs/arm-softmmu.mak |   1 +

>   hw/arm/Makefile.objs            |   1 +

>   hw/arm/nrf51_soc.c              | 119 ++++++++++++++++++++++++++++++++

>   include/hw/arm/nrf51_soc.h      |  42 +++++++++++

>   4 files changed, 163 insertions(+)

>   create mode 100644 hw/arm/nrf51_soc.c

>   create mode 100644 include/hw/arm/nrf51_soc.h

> 

> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak

> index e704cb6e34d7..3432721d7d08 100644

> --- a/default-configs/arm-softmmu.mak

> +++ b/default-configs/arm-softmmu.mak

> @@ -102,6 +102,7 @@ CONFIG_STM32F2XX_SYSCFG=y

>   CONFIG_STM32F2XX_ADC=y

>   CONFIG_STM32F2XX_SPI=y

>   CONFIG_STM32F205_SOC=y

> +CONFIG_NRF51_SOC=y

>   

>   CONFIG_CMSDK_APB_TIMER=y

>   CONFIG_CMSDK_APB_UART=y

> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs

> index b1e4f8f006aa..e31875ec69bc 100644

> --- a/hw/arm/Makefile.objs

> +++ b/hw/arm/Makefile.objs

> @@ -36,3 +36,4 @@ obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o

>   obj-$(CONFIG_IOTKIT) += iotkit.o

>   obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o

>   obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o

> +obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o

> diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c

> new file mode 100644

> index 000000000000..03fa1dfc7456

> --- /dev/null

> +++ b/hw/arm/nrf51_soc.c

> @@ -0,0 +1,119 @@

> +/*

> + * Nordic Semiconductor nRF51 SoC

> + * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf

> + *

> + * Copyright 2018 Joel Stanley <joel@jms.id.au>

> + *

> + * This code is licensed under the GPL version 2 or later.  See

> + * the COPYING file in the top-level directory.

> + */

> +

> +#include "qemu/osdep.h"

> +#include "qapi/error.h"

> +#include "qemu-common.h"

> +#include "hw/arm/arm.h"

> +#include "hw/sysbus.h"

> +#include "hw/boards.h"

> +#include "hw/devices.h"

> +#include "hw/misc/unimp.h"

> +#include "exec/address-spaces.h"

> +#include "sysemu/sysemu.h"

> +#include "qemu/log.h"

> +#include "cpu.h"

> +

> +#include "hw/arm/nrf51_soc.h"

> +

> +#define IOMEM_BASE      0x40000000

> +#define IOMEM_SIZE      0x20000000

> +

> +#define FICR_BASE       0x10000000

> +#define FICR_SIZE       0x000000fc

> +

> +#define FLASH_BASE      0x00000000

> +#define SRAM_BASE       0x20000000

> +

> +/* The size and base is for the NRF51822 part. If other parts

> + * are supported in the future, add a sub-class of NRF51SoC for

> + * the specific variants */

> +#define NRF51822_FLASH_SIZE     (256 * 1024)

> +#define NRF51822_SRAM_SIZE      (16 * 1024)

> +

> +static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)

> +{

> +    NRF51State *s = NRF51_SOC(dev_soc);

> +    Error *err = NULL;

> +

> +    if (!s->board_memory) {

> +        error_setg(errp, "memory property was not set");

> +        return;

> +    }

> +

> +    object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",

> +            &err);

> +    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);

> +

> +    memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);

> +

> +    memory_region_init_ram(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size,

> +            &err);

> +    if (err) {

> +        error_propagate(errp, err);

> +        return;

> +    }

> +    memory_region_set_readonly(&s->flash, true);

> +    memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash);

> +

> +    memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err);

> +    if (err) {

> +        error_propagate(errp, err);

> +        return;

> +    }

> +    memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);

> +

> +    create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);

> +    create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);

> +    create_unimplemented_device("nrf51_soc.private", 0xF0000000, 0x10000000);

> +}

> +

> +static void nrf51_soc_init(Object *obj)

> +{

> +    NRF51State *s = NRF51_SOC(obj);

> +

> +    memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);

> +

> +    object_initialize(&s->cpu, sizeof(s->cpu), TYPE_ARM_M_PROFILE);

> +    object_property_add_child(OBJECT(s), "armv6m", OBJECT(&s->cpu), &error_abort);

> +    qdev_set_parent_bus(DEVICE(&s->cpu), sysbus_get_default());

> +    qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m0"));

> +    qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 96);


Where did this number come from? ARMv6-M NVIC supports only 32 interrupts.

Best regards, Julia Suvorova.
Joel Stanley July 30, 2018, 2:02 p.m. UTC | #2 
On 26 July 2018 at 20:31, Julia Suvorova <jusual@mail.ru> wrote:

>> +++ b/hw/arm/nrf51_soc.c


>> +static void nrf51_soc_init(Object *obj)

>> +{

>> +    NRF51State *s = NRF51_SOC(obj);

>> +

>> +    memory_region_init(&s->container, obj, "nrf51-container",

>> UINT64_MAX);

>> +

>> +    object_initialize(&s->cpu, sizeof(s->cpu), TYPE_ARM_M_PROFILE);

>> +    object_property_add_child(OBJECT(s), "armv6m", OBJECT(&s->cpu),

>> &error_abort);

>> +    qdev_set_parent_bus(DEVICE(&s->cpu), sysbus_get_default());

>> +    qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",

>> ARM_CPU_TYPE_NAME("cortex-m0"));

>> +    qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 96);

>

>

> Where did this number come from? ARMv6-M NVIC supports only 32 interrupts.


I think this was left over from when I was first creating a m0 based
system (efm32hg) over a year ago. Good catch.

I couldn't see a table of valid interrupts in the nrf51 datasheet. Are
you able to find this information?

If not, I will re-spin with the number of irqs set to 32.

Cheers,

Joel
Xingtao Yao (Fujitsu)" via Aug. 2, 2018, 9:42 a.m. UTC | #3 
On 30.07.2018 17:02, Joel Stanley wrote:
> On 26 July 2018 at 20:31, Julia Suvorova <jusual@mail.ru> wrote:

> 

>>> +++ b/hw/arm/nrf51_soc.c

> 

>>> +static void nrf51_soc_init(Object *obj)

>>> +{

>>> +    NRF51State *s = NRF51_SOC(obj);

>>> +

>>> +    memory_region_init(&s->container, obj, "nrf51-container",

>>> UINT64_MAX);

>>> +

>>> +    object_initialize(&s->cpu, sizeof(s->cpu), TYPE_ARM_M_PROFILE);

>>> +    object_property_add_child(OBJECT(s), "armv6m", OBJECT(&s->cpu),

>>> &error_abort);

>>> +    qdev_set_parent_bus(DEVICE(&s->cpu), sysbus_get_default());

>>> +    qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",

>>> ARM_CPU_TYPE_NAME("cortex-m0"));

>>> +    qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 96);

>>

>>

>> Where did this number come from? ARMv6-M NVIC supports only 32 interrupts.

> 

> I think this was left over from when I was first creating a m0 based

> system (efm32hg) over a year ago. Good catch.

> 

> I couldn't see a table of valid interrupts in the nrf51 datasheet. Are

> you able to find this information?

> 

> If not, I will re-spin with the number of irqs set to 32.


The only information in the nRF51 Reference Manual is given in
paragraph 10.1.6:
A peripheral only occupies one interrupt, and the interrupt number
follows the peripheral ID, for example, the peripheral with ID=4 is
connected to interrupt number 4 in the Nested Vector Interrupt
Controller (NVIC).

Thus, Table 2 in 5.2 can be used as an interrupt table.

In any case, unextended ARMv6-M limits the number of interrupts to 32.
And efm32hg is based on M0+ and can have additional features.

Best regards, Julia Suvorova.
diff mbox series

Patch

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index e704cb6e34d7..3432721d7d08 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -102,6 +102,7 @@  CONFIG_STM32F2XX_SYSCFG=y
 CONFIG_STM32F2XX_ADC=y
 CONFIG_STM32F2XX_SPI=y
 CONFIG_STM32F205_SOC=y
+CONFIG_NRF51_SOC=y
 
 CONFIG_CMSDK_APB_TIMER=y
 CONFIG_CMSDK_APB_UART=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index b1e4f8f006aa..e31875ec69bc 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -36,3 +36,4 @@  obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
 obj-$(CONFIG_IOTKIT) += iotkit.o
 obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o
 obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o
+obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
new file mode 100644
index 000000000000..03fa1dfc7456
--- /dev/null
+++ b/hw/arm/nrf51_soc.c
@@ -0,0 +1,119 @@ 
+/*
+ * Nordic Semiconductor nRF51 SoC
+ * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
+ *
+ * Copyright 2018 Joel Stanley <joel@jms.id.au>
+ *
+ * This code is licensed under the GPL version 2 or later.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/arm.h"
+#include "hw/sysbus.h"
+#include "hw/boards.h"
+#include "hw/devices.h"
+#include "hw/misc/unimp.h"
+#include "exec/address-spaces.h"
+#include "sysemu/sysemu.h"
+#include "qemu/log.h"
+#include "cpu.h"
+
+#include "hw/arm/nrf51_soc.h"
+
+#define IOMEM_BASE      0x40000000
+#define IOMEM_SIZE      0x20000000
+
+#define FICR_BASE       0x10000000
+#define FICR_SIZE       0x000000fc
+
+#define FLASH_BASE      0x00000000
+#define SRAM_BASE       0x20000000
+
+/* The size and base is for the NRF51822 part. If other parts
+ * are supported in the future, add a sub-class of NRF51SoC for
+ * the specific variants */
+#define NRF51822_FLASH_SIZE     (256 * 1024)
+#define NRF51822_SRAM_SIZE      (16 * 1024)
+
+static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+    NRF51State *s = NRF51_SOC(dev_soc);
+    Error *err = NULL;
+
+    if (!s->board_memory) {
+        error_setg(errp, "memory property was not set");
+        return;
+    }
+
+    object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",
+            &err);
+    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
+
+    memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
+
+    memory_region_init_ram(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size,
+            &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    memory_region_set_readonly(&s->flash, true);
+    memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash);
+
+    memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);
+
+    create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);
+    create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);
+    create_unimplemented_device("nrf51_soc.private", 0xF0000000, 0x10000000);
+}
+
+static void nrf51_soc_init(Object *obj)
+{
+    NRF51State *s = NRF51_SOC(obj);
+
+    memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
+
+    object_initialize(&s->cpu, sizeof(s->cpu), TYPE_ARM_M_PROFILE);
+    object_property_add_child(OBJECT(s), "armv6m", OBJECT(&s->cpu), &error_abort);
+    qdev_set_parent_bus(DEVICE(&s->cpu), sysbus_get_default());
+    qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m0"));
+    qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 96);
+}
+
+static Property nrf51_soc_properties[] = {
+    DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+    DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
+    DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, NRF51822_FLASH_SIZE),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void nrf51_soc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = nrf51_soc_realize;
+    dc->props = nrf51_soc_properties;
+}
+
+static const TypeInfo nrf51_soc_info = {
+    .name          = TYPE_NRF51_SOC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(NRF51State),
+    .instance_init = nrf51_soc_init,
+    .class_init    = nrf51_soc_class_init,
+};
+
+static void nrf51_soc_types(void)
+{
+    type_register_static(&nrf51_soc_info);
+}
+type_init(nrf51_soc_types)
diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
new file mode 100644
index 000000000000..838bccd815df
--- /dev/null
+++ b/include/hw/arm/nrf51_soc.h
@@ -0,0 +1,42 @@ 
+/*
+ * Nordic Semiconductor nRF51  SoC
+ *
+ * Copyright 2018 Joel Stanley <joel@jms.id.au>
+ *
+ * This code is licensed under the GPL version 2 or later.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#ifndef NRF51_SOC_H
+#define NRF51_SOC_H
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/arm/arm-m-profile.h"
+
+#define TYPE_NRF51_SOC "nrf51-soc"
+#define NRF51_SOC(obj) \
+    OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC)
+
+typedef struct NRF51State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    ARMMProfileState cpu;
+
+    MemoryRegion iomem;
+    MemoryRegion sram;
+    MemoryRegion flash;
+
+    uint32_t sram_size;
+    uint32_t flash_size;
+
+    MemoryRegion *board_memory;
+
+    MemoryRegion container;
+
+} NRF51State;
+
+#endif
+