Message ID | 1530612152-27555-6-git-send-email-dkos@cadence.com |
---|---|
State | Superseded |
Headers | show
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[01/12] HACK: increase timeout for drm_atomic_helper_wait_for_vblanks
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diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 7f5d568..b6a27ab 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -370,10 +370,38 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) { u8 values[3]; int err; + unsigned int addr; memset(link, 0, sizeof(*link)); - err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values)); + /* + * DP 1.4 introduced a DP_EXTENDED_RCVR_CAPA_FIELD_PRESENT bit in + * DP_TRAINING_AUX_RD_INTERVAL register. If set, DPCD registers from + * DP_DPCD_REV to DP_ADAPTER_CAP should be retrieved starting from + * DP_DPCD_REV_EXTENDED. All registers are copied except DP_DPCD_REV, + * DP_MAX_LINK_RATE and DP_DOWNSTREAMPORT_PRESENT which represent the + * "true capabilities" of DPRX device. + * + * Original DP_DPCD_REV, DP_MAX_LINK_RATE and DP_DOWNSTREAMPORT_PRESENT + * might falsely return lower capabilities to "avoid interoperability + * issues with some of the existing DP Source devices that malfunction + * when they discover the higher capabilities within those three + * registers.". + * + * Before DP 1.4, DP_EXTENDED_RCVR_CAPA_FIELD_PRESENT bit was reserved + * and read 0 so it's safe to check against it even if DP revision is + * <1.4 + */ + err = drm_dp_dpcd_readb(aux, DP_TRAINING_AUX_RD_INTERVAL, values); + if (err < 0) + return err; + + if (values[0] & DP_EXTENDED_RCVR_CAPA_FIELD_PRESENT) + addr = DP_DP13_DPCD_REV; + else + addr = DP_DPCD_REV; + + err = drm_dp_dpcd_read(aux, addr, values, sizeof(values)); if (err < 0) return err;