diff mbox series

[edk2,edk2-platforms,v2,3/3] Hisilicon/D05: Support SBSA watchdog

Message ID 1520842578-95453-4-git-send-email-heyi.guo@linaro.org
State New
Headers show
Series Fix SBSA test failures on D05 | expand

Commit Message

gary guo March 12, 2018, 8:16 a.m. UTC 
From: Chenhui Sun <sunchenhui@huawei.com>


Add description of SBSA watchdogs to ACPI GTDT on D05.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chenhui Sun <sunchenhui@huawei.com>

Signed-off-by: Heyi Guo <heyi.guo@linaro.org>

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Graeme Gregory <graeme.gregory@linaro.org>
---

Notes:
    v2:
    - Use local defines instead of PCD+define for watchdog base address
      [Ard]

 Silicon/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 25 ++++++++++----------
 1 file changed, 13 insertions(+), 12 deletions(-)

-- 
2.7.4

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diff mbox series

Patch

diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc
index 2a9d209c00f0..9f27696cf022 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc
@@ -30,6 +30,14 @@ 
 
 #define GTDT_GTIMER_FLAGS           (GTDT_TIMER_ALWAYS_ON_CAPABILITY | GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
 
+// Generic watchdog address for SCCL (Super CPU cluster) A and SCCL B on Hi1616.
+// Watchdogs on socket 1 are not mapped to SPI interrupts so we can't describe
+// them in GTDT.
+#define GENERIC_WATCHDOG_CONTROL_BASE_SCCL_A 0x40500000
+#define GENERIC_WATCHDOG_REFRESH_BASE_SCCL_A 0x40600000
+#define GENERIC_WATCHDOG_CONTROL_BASE_SCCL_B 0x60500000
+#define GENERIC_WATCHDOG_REFRESH_BASE_SCCL_B 0x60600000
+
 #pragma pack (1)
 
 typedef struct {
@@ -57,22 +65,15 @@  EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
     FixedPcdGet32 (PcdArmArchTimerHypIntrNum),    // UINT32  NonSecurePL2TimerGSIV
     GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL2TimerFlags
     0xFFFFFFFFFFFFFFFF,                           // UINT64  CntReadBasePhysicalAddress
-#ifdef notyet
-    PV660_WATCHDOG_COUNT,                          // UINT32  PlatformTimerCount
+    HI1616_WATCHDOG_COUNT,                        // UINT32  PlatformTimerCount
     sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
   },
   {
-    EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
-        //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
-        0, 0, 0, 0),
-    EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
-        //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
-        0, 0, 0, 0)
+    EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+      GENERIC_WATCHDOG_REFRESH_BASE_SCCL_A, GENERIC_WATCHDOG_CONTROL_BASE_SCCL_A, 400, 0),
+    EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+      GENERIC_WATCHDOG_REFRESH_BASE_SCCL_B, GENERIC_WATCHDOG_CONTROL_BASE_SCCL_B, 496, 0)
   }
-#else /* !notyet */
-  0, 0
-  }
-#endif
   };
 
 //