| Message ID | 20180305160415.16760-8-andre.przywara@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | New VGIC(-v2) implementation | expand |
Hi Andre, On 05/03/18 16:03, Andre Przywara wrote: > The two central functions to synchronise our emulated VGIC state with > the GIC hardware (the LRs, really), are named somewhat confusingly. > Rename them from gic_inject() to vgic_sync_to_lrs() and from > gic_clear_lrs() to vgic_sync_from_lrs(), to make the code more readable. > > Signed-off-by: Andre Przywara <andre.przywara@linaro.org> Acked-by: Julien Grall <julien.grall@arm.com> Cheers, > --- > Changelog RFC ... v1: > - new patch > > xen/arch/arm/gic-vgic.c | 4 ++-- > xen/arch/arm/traps.c | 4 ++-- > xen/include/asm-arm/gic.h | 4 ++-- > 3 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c > index d273863556..c0fe38fd37 100644 > --- a/xen/arch/arm/gic-vgic.c > +++ b/xen/arch/arm/gic-vgic.c > @@ -247,7 +247,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) > } > } > > -void gic_clear_lrs(struct vcpu *v) > +void vgic_sync_from_lrs(struct vcpu *v) > { > int i = 0; > unsigned long flags; > @@ -377,7 +377,7 @@ out: > return rc; > } > > -void gic_inject(void) > +void vgic_sync_to_lrs(void) > { > ASSERT(!local_irq_is_enabled()); > > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c > index 1cba7e584d..7411bff7a7 100644 > --- a/xen/arch/arm/traps.c > +++ b/xen/arch/arm/traps.c > @@ -2024,7 +2024,7 @@ static void enter_hypervisor_head(struct cpu_user_regs *regs) > if ( current->arch.hcr_el2 & HCR_VA ) > current->arch.hcr_el2 = READ_SYSREG(HCR_EL2); > > - gic_clear_lrs(current); > + vgic_sync_from_lrs(current); > } > } > > @@ -2234,7 +2234,7 @@ void leave_hypervisor_tail(void) > { > local_irq_disable(); > if (!softirq_pending(smp_processor_id())) { > - gic_inject(); > + vgic_sync_to_lrs(); > > /* > * If the SErrors handle option is "DIVERSE", we have to prevent > diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h > index 497f195bc1..e2ae4254ed 100644 > --- a/xen/include/asm-arm/gic.h > +++ b/xen/include/asm-arm/gic.h > @@ -237,7 +237,7 @@ extern int gic_route_irq_to_guest(struct domain *, unsigned int virq, > int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, > struct irq_desc *desc); > > -extern void gic_inject(void); > +extern void vgic_sync_to_lrs(void); > extern void gic_clear_pending_irqs(struct vcpu *v); > extern int gic_events_need_delivery(void); > > @@ -295,7 +295,7 @@ extern unsigned int gic_number_lines(void); > /* IRQ translation function for the device tree */ > int gic_irq_xlate(const u32 *intspec, unsigned int intsize, > unsigned int *out_hwirq, unsigned int *out_type); > -void gic_clear_lrs(struct vcpu *v); > +void vgic_sync_from_lrs(struct vcpu *v); > > struct gic_info { > /* GIC version */ >
diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index d273863556..c0fe38fd37 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -247,7 +247,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) } } -void gic_clear_lrs(struct vcpu *v) +void vgic_sync_from_lrs(struct vcpu *v) { int i = 0; unsigned long flags; @@ -377,7 +377,7 @@ out: return rc; } -void gic_inject(void) +void vgic_sync_to_lrs(void) { ASSERT(!local_irq_is_enabled()); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 1cba7e584d..7411bff7a7 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2024,7 +2024,7 @@ static void enter_hypervisor_head(struct cpu_user_regs *regs) if ( current->arch.hcr_el2 & HCR_VA ) current->arch.hcr_el2 = READ_SYSREG(HCR_EL2); - gic_clear_lrs(current); + vgic_sync_from_lrs(current); } } @@ -2234,7 +2234,7 @@ void leave_hypervisor_tail(void) { local_irq_disable(); if (!softirq_pending(smp_processor_id())) { - gic_inject(); + vgic_sync_to_lrs(); /* * If the SErrors handle option is "DIVERSE", we have to prevent diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 497f195bc1..e2ae4254ed 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -237,7 +237,7 @@ extern int gic_route_irq_to_guest(struct domain *, unsigned int virq, int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, struct irq_desc *desc); -extern void gic_inject(void); +extern void vgic_sync_to_lrs(void); extern void gic_clear_pending_irqs(struct vcpu *v); extern int gic_events_need_delivery(void); @@ -295,7 +295,7 @@ extern unsigned int gic_number_lines(void); /* IRQ translation function for the device tree */ int gic_irq_xlate(const u32 *intspec, unsigned int intsize, unsigned int *out_hwirq, unsigned int *out_type); -void gic_clear_lrs(struct vcpu *v); +void vgic_sync_from_lrs(struct vcpu *v); struct gic_info { /* GIC version */
The two central functions to synchronise our emulated VGIC state with the GIC hardware (the LRs, really), are named somewhat confusingly. Rename them from gic_inject() to vgic_sync_to_lrs() and from gic_clear_lrs() to vgic_sync_from_lrs(), to make the code more readable. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> --- Changelog RFC ... v1: - new patch xen/arch/arm/gic-vgic.c | 4 ++-- xen/arch/arm/traps.c | 4 ++-- xen/include/asm-arm/gic.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-)