@@ -698,7 +698,7 @@ static u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
return mgr_desc[channel].sync_lost_irq;
}
-u32 dispc_wb_get_framedone_irq(void)
+static u32 dispc_wb_get_framedone_irq(void)
{
return DISPC_IRQ_FRAMEDONEWB;
}
@@ -730,12 +730,12 @@ static void dispc_mgr_go(enum omap_channel channel)
mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
}
-bool dispc_wb_go_busy(void)
+static bool dispc_wb_go_busy(void)
{
return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
}
-void dispc_wb_go(void)
+static void dispc_wb_go(void)
{
enum omap_plane_id plane = OMAP_DSS_WB;
bool enable, go;
@@ -2668,7 +2668,7 @@ static int dispc_ovl_setup(enum omap_plane_id plane,
return r;
}
-int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
+static int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
bool mem_to_mem, const struct videomode *vm,
enum dss_writeback_channel channel_in)
{
@@ -2750,6 +2750,11 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
return 0;
}
+static bool dispc_has_writeback(void)
+{
+ return dispc.feat->has_writeback;
+}
+
static int dispc_ovl_enable(enum omap_plane_id plane, bool enable)
{
DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
@@ -4553,6 +4558,12 @@ static const struct dispc_ops dispc_ops = {
.ovl_enable = dispc_ovl_enable,
.ovl_setup = dispc_ovl_setup,
.ovl_get_color_modes = dispc_ovl_get_color_modes,
+
+ .wb_get_framedone_irq = dispc_wb_get_framedone_irq,
+ .wb_setup = dispc_wb_setup,
+ .has_writeback = dispc_has_writeback,
+ .wb_go_busy = dispc_wb_go_busy,
+ .wb_go = dispc_wb_go,
};
/* DISPC HW IP initialisation */
@@ -97,17 +97,6 @@ enum dss_dsi_content_type {
DSS_DSI_CONTENT_GENERIC,
};
-enum dss_writeback_channel {
- DSS_WB_LCD1_MGR = 0,
- DSS_WB_LCD2_MGR = 1,
- DSS_WB_TV_MGR = 2,
- DSS_WB_OVL0 = 3,
- DSS_WB_OVL1 = 4,
- DSS_WB_OVL2 = 5,
- DSS_WB_OVL3 = 6,
- DSS_WB_LCD3_MGR = 7,
-};
-
enum dss_clk_source {
DSS_CLK_SRC_FCK = 0,
@@ -380,14 +369,6 @@ int dispc_mgr_get_clock_div(enum omap_channel channel,
struct dispc_clock_info *cinfo);
void dispc_set_tv_pclk(unsigned long pclk);
-u32 dispc_wb_get_framedone_irq(void);
-bool dispc_wb_go_busy(void);
-void dispc_wb_go(void);
-void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
-int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
- bool mem_to_mem, const struct videomode *vm,
- enum dss_writeback_channel channel_in);
-
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
static inline void dss_collect_irq_stats(u32 irqstatus, unsigned int *irq_arr)
{
@@ -618,6 +618,17 @@ void omapdss_set_is_initialized(bool set);
struct device_node *dss_of_port_get_parent_device(struct device_node *port);
u32 dss_of_port_get_port_number(struct device_node *port);
+enum dss_writeback_channel {
+ DSS_WB_LCD1_MGR = 0,
+ DSS_WB_LCD2_MGR = 1,
+ DSS_WB_TV_MGR = 2,
+ DSS_WB_OVL0 = 3,
+ DSS_WB_OVL1 = 4,
+ DSS_WB_OVL2 = 5,
+ DSS_WB_OVL3 = 6,
+ DSS_WB_LCD3_MGR = 7,
+};
+
struct dss_mgr_ops {
int (*connect)(enum omap_channel channel,
struct omap_dss_device *dst);
@@ -700,6 +711,14 @@ struct dispc_ops {
enum omap_channel channel);
const u32 *(*ovl_get_color_modes)(enum omap_plane_id plane);
+
+ u32 (*wb_get_framedone_irq)(void);
+ int (*wb_setup)(const struct omap_dss_writeback_info *wi,
+ bool mem_to_mem, const struct videomode *vm,
+ enum dss_writeback_channel channel_in);
+ bool (*has_writeback)(void);
+ bool (*wb_go_busy)(void);
+ void (*wb_go)(void);
};
void dispc_set_ops(const struct dispc_ops *o);
Add writeback specific dispc functions to dispc_ops so that omapdrm can use them. Also move 'enum dss_writeback_channel' to the public omapdss.h for omapdrm. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> --- drivers/gpu/drm/omapdrm/dss/dispc.c | 19 +++++++++++++++---- drivers/gpu/drm/omapdrm/dss/dss.h | 19 ------------------- drivers/gpu/drm/omapdrm/dss/omapdss.h | 19 +++++++++++++++++++ 3 files changed, 34 insertions(+), 23 deletions(-)