| Message ID | 20180207111729.15737-6-ard.biesheuvel@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target-arm: add SHA-3, SM3 and SHA512 instruction support | expand |
Ard Biesheuvel <ard.biesheuvel@linaro.org> writes: > Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to > AArch64 user mode emulation. Are you aware of any processors with ARMv8.2 available yet? It might be nice to have a more recent model for system emulation and the pieces seems to be coming together. > > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > --- > linux-user/elfload.c | 19 +++++++++++++++++++ > target/arm/cpu64.c | 4 ++++ > 2 files changed, 23 insertions(+) > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index 20f3d8c2c373..7922ab8eab79 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -512,6 +512,21 @@ enum { > ARM_HWCAP_A64_SHA1 = 1 << 5, > ARM_HWCAP_A64_SHA2 = 1 << 6, > ARM_HWCAP_A64_CRC32 = 1 << 7, > + ARM_HWCAP_A64_ATOMICS = 1 << 8, > + ARM_HWCAP_A64_FPHP = 1 << 9, > + ARM_HWCAP_A64_ASIMDHP = 1 << 10, > + ARM_HWCAP_A64_CPUID = 1 << 11, > + ARM_HWCAP_A64_ASIMDRDM = 1 << 12, > + ARM_HWCAP_A64_JSCVT = 1 << 13, > + ARM_HWCAP_A64_FCMA = 1 << 14, > + ARM_HWCAP_A64_LRCPC = 1 << 15, > + ARM_HWCAP_A64_DCPOP = 1 << 16, > + ARM_HWCAP_A64_SHA3 = 1 << 17, > + ARM_HWCAP_A64_SM3 = 1 << 18, > + ARM_HWCAP_A64_SM4 = 1 << 19, > + ARM_HWCAP_A64_ASIMDDP = 1 << 20, > + ARM_HWCAP_A64_SHA512 = 1 << 21, > + ARM_HWCAP_A64_SVE = 1 << 22, > }; > > #define ELF_HWCAP get_elf_hwcap() > @@ -532,6 +547,10 @@ static uint32_t get_elf_hwcap(void) > GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); > GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); > GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); > + GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3); > + GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3); > + GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4); > + GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); > #undef GET_FEATURE > > return hwcaps; > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 670c07ab6ed4..1c330adc281b 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -224,6 +224,10 @@ static void aarch64_any_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_V8_AES); > set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); > set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); > + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); > + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); > + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); > + set_feature(&cpu->env, ARM_FEATURE_V8_SM4); > set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); > set_feature(&cpu->env, ARM_FEATURE_CRC); > cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ -- Alex Bennée
On 7 February 2018 at 11:49, Alex Bennée <alex.bennee@linaro.org> wrote: > > Ard Biesheuvel <ard.biesheuvel@linaro.org> writes: > >> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to >> AArch64 user mode emulation. > > Are you aware of any processors with ARMv8.2 available yet? It might be > nice to have a more recent model for system emulation and the pieces > seems to be coming together. > I think Peter's idea was to have so kind of 'max' cpu type that enables all optional extensions in system emulation mode. AFAIK none of the Cortex-Axx cores that are public are available with these crypto features. >> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> >> --- >> linux-user/elfload.c | 19 +++++++++++++++++++ >> target/arm/cpu64.c | 4 ++++ >> 2 files changed, 23 insertions(+) >> >> diff --git a/linux-user/elfload.c b/linux-user/elfload.c >> index 20f3d8c2c373..7922ab8eab79 100644 >> --- a/linux-user/elfload.c >> +++ b/linux-user/elfload.c >> @@ -512,6 +512,21 @@ enum { >> ARM_HWCAP_A64_SHA1 = 1 << 5, >> ARM_HWCAP_A64_SHA2 = 1 << 6, >> ARM_HWCAP_A64_CRC32 = 1 << 7, >> + ARM_HWCAP_A64_ATOMICS = 1 << 8, >> + ARM_HWCAP_A64_FPHP = 1 << 9, >> + ARM_HWCAP_A64_ASIMDHP = 1 << 10, >> + ARM_HWCAP_A64_CPUID = 1 << 11, >> + ARM_HWCAP_A64_ASIMDRDM = 1 << 12, >> + ARM_HWCAP_A64_JSCVT = 1 << 13, >> + ARM_HWCAP_A64_FCMA = 1 << 14, >> + ARM_HWCAP_A64_LRCPC = 1 << 15, >> + ARM_HWCAP_A64_DCPOP = 1 << 16, >> + ARM_HWCAP_A64_SHA3 = 1 << 17, >> + ARM_HWCAP_A64_SM3 = 1 << 18, >> + ARM_HWCAP_A64_SM4 = 1 << 19, >> + ARM_HWCAP_A64_ASIMDDP = 1 << 20, >> + ARM_HWCAP_A64_SHA512 = 1 << 21, >> + ARM_HWCAP_A64_SVE = 1 << 22, >> }; >> >> #define ELF_HWCAP get_elf_hwcap() >> @@ -532,6 +547,10 @@ static uint32_t get_elf_hwcap(void) >> GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); >> GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); >> GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); >> + GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3); >> + GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3); >> + GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4); >> + GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); >> #undef GET_FEATURE >> >> return hwcaps; >> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c >> index 670c07ab6ed4..1c330adc281b 100644 >> --- a/target/arm/cpu64.c >> +++ b/target/arm/cpu64.c >> @@ -224,6 +224,10 @@ static void aarch64_any_initfn(Object *obj) >> set_feature(&cpu->env, ARM_FEATURE_V8_AES); >> set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); >> set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); >> + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); >> + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); >> + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); >> + set_feature(&cpu->env, ARM_FEATURE_V8_SM4); >> set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); >> set_feature(&cpu->env, ARM_FEATURE_CRC); >> cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ > > > -- > Alex Bennée
On Wed, Feb 7, 2018 at 12:53 PM, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote: > On 7 February 2018 at 11:49, Alex Bennée <alex.bennee@linaro.org> wrote: >> >> Ard Biesheuvel <ard.biesheuvel@linaro.org> writes: >> >>> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to >>> AArch64 user mode emulation. >> >> Are you aware of any processors with ARMv8.2 available yet? It might be >> nice to have a more recent model for system emulation and the pieces >> seems to be coming together. >> > > I think Peter's idea was to have so kind of 'max' cpu type that > enables all optional extensions in system emulation mode. > AFAIK none of the Cortex-Axx cores that are public are available with > these crypto features. Cortex-A75 is ARMv8.2. It should be available in devices this year. HTH, Laurent
On 7 February 2018 at 11:57, Laurent Desnogues <laurent.desnogues@gmail.com> wrote: > On Wed, Feb 7, 2018 at 12:53 PM, Ard Biesheuvel > <ard.biesheuvel@linaro.org> wrote: >> On 7 February 2018 at 11:49, Alex Bennée <alex.bennee@linaro.org> wrote: >>> >>> Ard Biesheuvel <ard.biesheuvel@linaro.org> writes: >>> >>>> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to >>>> AArch64 user mode emulation. >>> >>> Are you aware of any processors with ARMv8.2 available yet? It might be >>> nice to have a more recent model for system emulation and the pieces >>> seems to be coming together. >>> >> >> I think Peter's idea was to have so kind of 'max' cpu type that >> enables all optional extensions in system emulation mode. >> AFAIK none of the Cortex-Axx cores that are public are available with >> these crypto features. > > Cortex-A75 is ARMv8.2. It should be available in devices this year. > Yeah, but according to the docs on infocenter.arm.com, it does not implement the newer crypto instructions.
Ard Biesheuvel <ard.biesheuvel@linaro.org> writes: > Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to > AArch64 user mode emulation. So another problem I've come across is I can't turn this off. I ended up doing that in my FP16 series because otherwise existing RISU tests get broken. However having an optional flag for each little set of instructions seems overkill. Have you run any RISU tests? If you want you can add this to the aarch64.risu to generate some test patterns. # These are optional ARMv8.2 cryptographic extensions @v8.2,Cryptographic,CryptographicSHA # Cryptographic three-register SHA 512 # 31 21 20 16 15 14 13 12 11 10 9 5 4 0 # 11001110011 Rm 1 O 0 0 opcode Rn Rd SHA512H A64_V 1100 1110 011 rm:5 1 0 00 00 rn:5 rd:5 SHA512H2 A64_V 1100 1110 011 rm:5 1 0 00 01 rn:5 rd:5 SHA512SUI A64_V 1100 1110 011 rm:5 1 0 00 10 rn:5 rd:5 RAX1 A64_V 1100 1110 011 rm:5 1 0 00 11 rn:5 rd:5 SM3PARTW1 A64_V 1100 1110 011 rm:5 1 1 00 00 rn:5 rd:5 SM3PARTW2 A64_V 1100 1110 011 rm:5 1 1 00 01 rn:5 rd:5 SM4 A64_V 1100 1110 011 rm:5 1 1 00 10 rn:5 rd:5 # Cryptographic four-register # 31 23 22 21 20 16 15 14 10 9 5 4 0 # 1100 1110 0 Op0 Rm 0 Ra Rn Rd EOR3 A64_V 1110 1110 0 00 rm:5 0 ra:5 rn:5 rd:5 BCAX A64_V 1110 1110 0 01 rm:5 0 ra:5 rn:5 rd:5 SM3SS1 A64_V 1110 1110 0 10 rm:5 0 ra:5 rn:5 rd:5 # Cryptographic two-register SHA 512 # 31 12 11 10 9 5 4 0 # 1100 1110 1100 0000 1000 op Rn Rd SHA512SU0 A64_V 1100 1110 1100 0000 1000 00 rn:5 rd:5 SM4E A64_V 1100 1110 1100 0000 1000 01 rn:5 rd:5 @ > > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > --- > linux-user/elfload.c | 19 +++++++++++++++++++ > target/arm/cpu64.c | 4 ++++ > 2 files changed, 23 insertions(+) > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index 20f3d8c2c373..7922ab8eab79 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -512,6 +512,21 @@ enum { > ARM_HWCAP_A64_SHA1 = 1 << 5, > ARM_HWCAP_A64_SHA2 = 1 << 6, > ARM_HWCAP_A64_CRC32 = 1 << 7, > + ARM_HWCAP_A64_ATOMICS = 1 << 8, > + ARM_HWCAP_A64_FPHP = 1 << 9, > + ARM_HWCAP_A64_ASIMDHP = 1 << 10, > + ARM_HWCAP_A64_CPUID = 1 << 11, > + ARM_HWCAP_A64_ASIMDRDM = 1 << 12, > + ARM_HWCAP_A64_JSCVT = 1 << 13, > + ARM_HWCAP_A64_FCMA = 1 << 14, > + ARM_HWCAP_A64_LRCPC = 1 << 15, > + ARM_HWCAP_A64_DCPOP = 1 << 16, > + ARM_HWCAP_A64_SHA3 = 1 << 17, > + ARM_HWCAP_A64_SM3 = 1 << 18, > + ARM_HWCAP_A64_SM4 = 1 << 19, > + ARM_HWCAP_A64_ASIMDDP = 1 << 20, > + ARM_HWCAP_A64_SHA512 = 1 << 21, > + ARM_HWCAP_A64_SVE = 1 << 22, > }; > > #define ELF_HWCAP get_elf_hwcap() > @@ -532,6 +547,10 @@ static uint32_t get_elf_hwcap(void) > GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); > GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); > GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); > + GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3); > + GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3); > + GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4); > + GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); > #undef GET_FEATURE > > return hwcaps; > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 670c07ab6ed4..1c330adc281b 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -224,6 +224,10 @@ static void aarch64_any_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_V8_AES); > set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); > set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); > + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); > + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); > + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); > + set_feature(&cpu->env, ARM_FEATURE_V8_SM4); > set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); > set_feature(&cpu->env, ARM_FEATURE_CRC); > cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ -- Alex Bennée
On 7 February 2018 at 14:57, Alex Bennée <alex.bennee@linaro.org> wrote: > > Ard Biesheuvel <ard.biesheuvel@linaro.org> writes: > >> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to >> AArch64 user mode emulation. > > So another problem I've come across is I can't turn this off. I ended up > doing that in my FP16 series because otherwise existing RISU tests get > broken. However having an optional flag for each little set of > instructions seems overkill. Why do the existing tests break? Are they checking UNDEF for previously-reserved bits of the encoding space? > Have you run any RISU tests? If you want you can add this to the > aarch64.risu to generate some test patterns. I wrote some risu patterns for testing these. I was going to send the patch out tomorrow... (I used the tag A64_C82 rather than A64_V.) thanks -- PMM
Peter Maydell <peter.maydell@linaro.org> writes: > On 7 February 2018 at 14:57, Alex Bennée <alex.bennee@linaro.org> wrote: >> >> Ard Biesheuvel <ard.biesheuvel@linaro.org> writes: >> >>> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to >>> AArch64 user mode emulation. >> >> So another problem I've come across is I can't turn this off. I ended up >> doing that in my FP16 series because otherwise existing RISU tests get >> broken. However having an optional flag for each little set of >> instructions seems overkill. > > Why do the existing tests break? Are they checking UNDEF > for previously-reserved bits of the encoding space? Yeah. Maybe the easiest solution is to find the undefs and re-generate everything. > >> Have you run any RISU tests? If you want you can add this to the >> aarch64.risu to generate some test patterns. > > I wrote some risu patterns for testing these. I was going > to send the patch out tomorrow... > > (I used the tag A64_C82 rather than A64_V.) Ohh that is a useful use for that tag... > > thanks > -- PMM -- Alex Bennée
diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 20f3d8c2c373..7922ab8eab79 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -512,6 +512,21 @@ enum { ARM_HWCAP_A64_SHA1 = 1 << 5, ARM_HWCAP_A64_SHA2 = 1 << 6, ARM_HWCAP_A64_CRC32 = 1 << 7, + ARM_HWCAP_A64_ATOMICS = 1 << 8, + ARM_HWCAP_A64_FPHP = 1 << 9, + ARM_HWCAP_A64_ASIMDHP = 1 << 10, + ARM_HWCAP_A64_CPUID = 1 << 11, + ARM_HWCAP_A64_ASIMDRDM = 1 << 12, + ARM_HWCAP_A64_JSCVT = 1 << 13, + ARM_HWCAP_A64_FCMA = 1 << 14, + ARM_HWCAP_A64_LRCPC = 1 << 15, + ARM_HWCAP_A64_DCPOP = 1 << 16, + ARM_HWCAP_A64_SHA3 = 1 << 17, + ARM_HWCAP_A64_SM3 = 1 << 18, + ARM_HWCAP_A64_SM4 = 1 << 19, + ARM_HWCAP_A64_ASIMDDP = 1 << 20, + ARM_HWCAP_A64_SHA512 = 1 << 21, + ARM_HWCAP_A64_SVE = 1 << 22, }; #define ELF_HWCAP get_elf_hwcap() @@ -532,6 +547,10 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); + GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3); + GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3); + GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4); + GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); #undef GET_FEATURE return hwcaps; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6ed4..1c330adc281b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -224,6 +224,10 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_AES); set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM4); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to AArch64 user mode emulation. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- linux-user/elfload.c | 19 +++++++++++++++++++ target/arm/cpu64.c | 4 ++++ 2 files changed, 23 insertions(+) -- 2.11.0