diff mbox series

[Xen-devel,9/9] xen/arm: Help to know the hardening provided for a CPU

Message ID 20180205132011.27996-10-julien.grall@arm.com
State New
Headers show
Series xen/arm: PSCI 1.1 and SMCCC-1.1 support and XSA-254 variant 2 update | expand

Commit Message

Julien Grall Feb. 5, 2018, 1:20 p.m. UTC 
---
 xen/arch/arm/cpuerrata.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

Comments

Julien Grall Feb. 5, 2018, 1:25 p.m. UTC | #1 
Hmmm sorry, I was not meant to be sent with this series. I will resend 
it separately with a proper commit message.

On 05/02/18 13:20, Julien Grall wrote:
> ---
>   xen/arch/arm/cpuerrata.c | 9 +++++++--
>   1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
> index 9c7458ef06..6704648b26 100644
> --- a/xen/arch/arm/cpuerrata.c
> +++ b/xen/arch/arm/cpuerrata.c
> @@ -79,7 +79,8 @@ static bool copy_hyp_vect_bpi(unsigned int slot, const char *hyp_vec_start,
>   static bool __maybe_unused
>   install_bp_hardening_vec(const struct arm_cpu_capabilities *entry,
>                            const char *hyp_vec_start,
> -                         const char *hyp_vec_end)
> +                         const char *hyp_vec_end,
> +                         const char *desc)
>   {
>       static int last_slot = -1;
>       static DEFINE_SPINLOCK(bp_lock);
> @@ -94,6 +95,9 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry,
>       if ( !entry->matches(entry) )
>           return true;
>   
> +    printk(XENLOG_INFO "CPU%u will %s on exception entry\n",
> +           smp_processor_id(), desc);
> +
>       /*
>        * No need to install hardened vector when the processor has
>        * ID_AA64PRF0_EL1.CSV2 set.
> @@ -157,7 +161,8 @@ static int enable_psci_bp_hardening(void *data)
>        */
>       if ( psci_ver >= PSCI_VERSION(0, 2) )
>           ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start,
> -                                       __psci_hyp_bp_inval_end);
> +                                       __psci_hyp_bp_inval_end,
> +                                       "call PSCI get version");
>       else if ( !warned )
>       {
>           ASSERT(system_state < SYS_STATE_active);
>
diff mbox series

Patch

diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
index 9c7458ef06..6704648b26 100644
--- a/xen/arch/arm/cpuerrata.c
+++ b/xen/arch/arm/cpuerrata.c
@@ -79,7 +79,8 @@  static bool copy_hyp_vect_bpi(unsigned int slot, const char *hyp_vec_start,
 static bool __maybe_unused
 install_bp_hardening_vec(const struct arm_cpu_capabilities *entry,
                          const char *hyp_vec_start,
-                         const char *hyp_vec_end)
+                         const char *hyp_vec_end,
+                         const char *desc)
 {
     static int last_slot = -1;
     static DEFINE_SPINLOCK(bp_lock);
@@ -94,6 +95,9 @@  install_bp_hardening_vec(const struct arm_cpu_capabilities *entry,
     if ( !entry->matches(entry) )
         return true;
 
+    printk(XENLOG_INFO "CPU%u will %s on exception entry\n",
+           smp_processor_id(), desc);
+
     /*
      * No need to install hardened vector when the processor has
      * ID_AA64PRF0_EL1.CSV2 set.
@@ -157,7 +161,8 @@  static int enable_psci_bp_hardening(void *data)
      */
     if ( psci_ver >= PSCI_VERSION(0, 2) )
         ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start,
-                                       __psci_hyp_bp_inval_end);
+                                       __psci_hyp_bp_inval_end,
+                                       "call PSCI get version");
     else if ( !warned )
     {
         ASSERT(system_state < SYS_STATE_active);